Philips Semiconductors

Application note

AN460

Using the P82B96 for bus interface

2001 Feb 14

6

Terminology

device must be bi-directional. So inputs are also outputs. Describing

a buffer operation without reference to ‘input’ and ‘output’ signals

presents difficulties: forgive the occasional use of these descriptions.

We also make assumptions about the possible system connections

to the chip, but these should not be taken to imply restrictions. In

many of the applications described it would also be possible to

We intend that this I/O pin will mostly be connected to a normal 5V

as OM4151 or OM1016. While this I/O pin is COMPATIBLE with

pin are non-standard.

Tx, Rx, and Ty, Ry: the buffered side

The other side of the chip features the separated input and output

pins Tx and Rx. While that provides the possibility to include

opto-couplers or to interface to other bus systems, in many

applications those two pins will simply be linked together to form an

product. We refer to the linked Rx/Tx I/O as the ‘buffered’ bus side.

This buffered I/O is intended for connection into all the unusual bus

systems — anything from 2 V to 15 V, with currents from microamps

to 30 mA static sink, and conventional 0.4 V saturation. Its input

Comparison between the P82B96 and the P82B715

bus extender

bus loading on one input does not influence the load to be driven by

devices connected to the corresponding ‘buffered’ output. While the

connection, opto-coupling the buffered signals allows connection to

and 5).

This is not the case in the P82B715 bus extender, which operates

by providing linear x10 current amplification of the bus current sink

capability in one direction only. Its two sides are linked by an internal

30

Ω resistor. This means that the loading on one side of the chip is

always part of the loading seen at the other side. It does not allow

different logic levels between busses having different voltages. The

bus voltages on each side of P82B715 are always matched within

100 mV.

The P82B96 is not pin-compatible with the P82B715, but its 30 mA

static sink capability will overlap some P82B715 applications.

P82B96 can also directly drive the 10x load that P82B715

drives — and P82B96 extends operation down to 2 V supply.

P82B96 FEATURES

Buffered bus drive capability

The 30 mA buffered bus static sink capability is useful when driving

opto-couplers.

It is also possible to drive low impedance, high voltage, long busses

directly from the P82B96, but the overall performance will be

dependent on the characteristics of the bus and it is difficult to fully

address this in the specifications for the P82B96.

1. The 30 mA Tx and Ty outputs do not guarantee full 100 kHz

operation when directly driving a long, high voltage bus. This is

because a 15 V supply and 30 mA static drive implies a

minimum pull-up resistor of 500

Ω. With 500Ω, a 4 nF bus load

means a time-constant of 2

risetime specification.

On 5 V, the 30 mA drive permits a pull-up of 167

Ω, so the time

constant with a 4 nF bus load easily permits full 100 kHz

operation.

Typically, applications for long, high voltage, busses will use low

speeds. For example the clock speed will usually be chosen

lower than 30 kHz when working with a bus longer than 100

meters.

2. If the buffered side is used to directly drive long wires then

‘ringing’ on the output bus becomes a possibility, with a strong

probability that the I/O pin will be driven below the ground

potential.

The P82B96 does not allow I/O pins to be driven below ground

or above 15 V. Therefore for long, ‘dirty’ busses we recommend

the use of external schottky diode and zener clamps (Figure 7).

Table 1. Table of drive capability

Type of application

Will drive bus load

To guaranteed clock

100 kHz

Low impedance 5 V

1/10 R and 10*C (4 nF)

100 kHz

3.3 V

±10% bus

100 kHz

Low impedance 3.3 V

1/10 normal R, 10*C

100 kHz

SMB bus (350

µA)

All SMB loads

normal SMB specs

15 V bus, 500

Ω

< 2 nF

100 kHz

15 V bus > 500

Ω

> 2 nF

depends on capacitance