Extra Low Capacitance for Integrated ESD

Mechanical Data

Notes

Dice size

Wafer size

4” (Gross die:27,500pcs/Good die>25,575pcs)

Chip Thickness

(A)138um±12um (B)470um±20um

Scribe line width

60um

Top metal

Al/Au/Ag

Back side metal

Al/Au/Ag/Sn

Parameter

Symbol

Conditions

Value

Unit

Reverse stand-off voltage

5.0

V

Peak pulse power

Tp=8/20us

150**

W

Peak pulse current

Tp=8/20us

5.0**

A

Electrostatic discharge

IEC61000-4-2

Level 4

± 15(AIR)

KV

Max.junction temp.

+150

℃

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

Breakdown voltage

Pin 5 to 2

6.1

8.0

8.5

V

Reverse leakage current

Pin 1,3,4,5,6 to 2

0.9

uA

Forward Voltage

Pin2 to Pin1,3,4,5,6

0.95

V

Clamping Voltage

15.0

28.0

V

Diode capacitance I/O-GND

0.8

pf

Diode capacitance I/O-I/O

0.4

pf

Characteristics TA=25℃

Notes:

(1)sampling testing:no bad dice inking/guaranteed good die >93%

(2)Testing follow customer

(3)Tj=Ta+Rth(j-a)*(pf+pr),where Rth(j-a)-thermal resistance,Pf-forward power dissipation,

Pr-revers power dissipation

(4)**For device testing

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