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ISP1161A1 Datasheet(PDF) 22 Page - NXP Semiconductors |
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ISP1161A1 Datasheet(HTML) 22 Page - NXP Semiconductors |
22 / 136 page Philips Semiconductors ISP1161A1 USB single-chip host and device controller Product data Rev. 03 — 23 December 2004 22 of 136 9397 750 13961 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. In isochronous mode, an interrupt is issued upon each packet transaction. The firmware must take care of timing synchronization with the host. This can be done via the Pseudo Start-Of-Frame (PSOF) interrupt, enabled via bit IEPSOF in the DcInterruptEnable register. If a Start-Of-Frame is lost, PSOF interrupts are generated every 1 ms. This allows the firmware to keep data transfer synchronized with the host. After 3 missed SOF events, the DC will enter ‘suspend’ state. An alternative way of handling isochronous data transfer is to enable both the SOF and the PSOF interrupts and disable the interrupt for each isochronous endpoint. Interrupt control: Bit INTENA in the DcMode register is a global enable/disable bit. The behavior of this bit is given in Figure 22. Fig 21. DC interrupt logic. Pin INT2: HIGH = de-assert; LOW = assert (individual interrupts are enabled). Fig 22. Behavior of bit INTENA. MGT946 RESET SUSPND RESUME SOF EP14 ... EP0IN .. . .. . .. . .. . EP0OUT EOT IERST DcInterrupt register DcInterruptEnable register IESUSP IERESM IESOF IEP14 ... IEP0IN IEP0OUT IEEOT DcMode register INTENA INT2 LATCH LE INT2 pin 004aaa198 INTENA = 0 SOF asserted INTENA = 1 SOF asserted INTENA = 0 (during this time, an interrupt event occurs. For example, SOF asserted.) A B C |
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