ISP1161A1 datasheet(75/136 Pages) PHILIPS

Part #	ISP1161A1

Description	Universal Serial Bus single-chip host and device controller

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Manufacturer	PHILIPS [NXP Semiconductors]

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Philips Semiconductors

ISP1161A1

USB single-chip host and device controller

Product data

Rev. 03 — 23 December 2004

75 of 136

9397 750 13961

10.6.6

HcITLBufferPort register (R/W: 40H/C0H)

This is the ITL buffer RAM read/write port. The bits 15 to 8 contain the data byte that

comes from the ITL buffer RAM’s even address. The bits 7 to 0 contain the data byte

that comes from the ITL buffer RAM’s odd address.

Code (Hex): 40 — read

Code (Hex): C0 — write

The HCD must set the byte count into the HcTransferCounter register and check the

HcBufferStatus register before reading from or writing to the buffer. The HCD must

write the command (40H to read, C0H to write) once only, and then read or write both

bytes of the data word. After every read/write, the pointer of ITL buffer RAM will be

automatically increased by two to point to the next data word until it reaches the value

of the HcTransferCounter register; otherwise, an internal EOT signal is not generated

to set bit 2 (AllEOTInterrupt) of the Hc

µPInterrupt register and update the

HcBufferStatus register.

The HCD must take care of the fact that the internal buffer RAM is organized in bytes.

The HCD must write the byte count into the HcTransferCounter register, but the HCD

reads or writes the buffer RAM by 16 bits (by 1 data word).

10.6.7

HcATLBufferPort register (R/W: 41H/C1H)

This is the ATL buffer RAM read/write port. Bits 15 to 8 contain the data byte that

comes from the Acknowledged Transfer List (ATL) buffer RAM’s odd address.

Bits 7 to 0 contain the data byte that comes from the ATL buffer RAM’s even address.

Code (Hex): 41 — read

Code (Hex): C1 — write

Table 62:

HcITLBufferPort register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

DataWord[15:8]

Reset

00H

Access

R/W

Bit

7

6

5

4

3

2

1

0

Symbol

DataWord[7:0]

Reset

00H

Access

R/W

Table 63:

HcITLBufferPort register: bit description

Bit

Symbol

Description

15 to 0

DataWord[15:0]

read/write ITL buffer RAM’s two data bytes.

Table 64:

HcATLBufferPort register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

DataWord[15:8]

Reset

00H

Access

R/W

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