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IDT70V3569S6BCI Datasheet(PDF) 10 Page - Integrated Device Technology |
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IDT70V3569S6BCI Datasheet(HTML) 10 Page - Integrated Device Technology |
10 / 16 page 6.42 IDT70V3569S High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges 10 AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing)(1,2) (VDD = 3.3V ± 150mV, TA = 0°C to +70°C) NOTES: 1. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable ( OE). 2. These values are valid for either level of VDDQ (3.3V/2.5V). See page 4 for details on selecting the desired I/O voltage levels for each port. 70V3569S4 Com'l Only 70V3569S5 Com'l & Ind 70V3569S6 Com'l & Ind Unit Symbol Parameter Min.Max.Min.Max.Min.Max. tCYC2 Clock Cycle Time (Pipelined) 7.5 ____ 10 ____ 12 ____ ns tCH2 Clock High Time (Pipelined) 3 ____ 4 ____ 5 ____ ns tCL2 Clock Low Time (Pipelined) 3 ____ 4 ____ 5 ____ ns tR Clock Rise Time ____ 3 ____ 3 ____ 3ns tF Clock Fall Time ____ 3 ____ 3 ____ 3ns tSA Address Setup Time 1.8 ____ 2.0 ____ 2.0 ____ ns tHA Address Hold Time 0.7 ____ 0.7 ____ 1.0 ____ ns tSC Chip Enable Setup Time 1.8 ____ 2.0 ____ 2.0 ____ ns tHC Chip Enable Hold Time 0.7 ____ 0.7 ____ 1.0 ____ ns tSB Byte Enable Setup Time 1.8 ____ 2.0 ____ 2.0 ____ ns tHB Byte Enable Hold Time 0.7 ____ 0.7 ____ 1.0 ____ ns tSW R/ W Setup Time 1.8 ____ 2.0 ____ 2.0 ____ ns tHW R/ W Hold Time 0.7 ____ 0.7 ____ 1.0 ____ ns tSD Input Data Setup Time 1.8 ____ 2.0 ____ 2.0 ____ ns tHD Input Data Hold Time 0.7 ____ 0.7 ____ 1.0 ____ ns tSAD ADS Setup Time 1.8 ____ 2.0 ____ 2.0 ____ ns tHAD ADS Hold Time 0.7 ____ 0.7 ____ 1.0 ____ ns tSCN CNTEN Setup Time 1.8 ____ 2.0 ____ 2.0 ____ ns tHCN CNTEN Hold Time 0.7 ____ 0.7 ____ 1.0 ____ ns tSRST CNTRST Setup Time 1.8 ____ 2.0 ____ 2.0 ____ ns tHRST CNTRST Hold Time 0.7 ____ 0.7 ____ 1.0 ____ ns tOE (1) Output Enable to Data Valid ____ 4 ____ 5 ____ 6ns tOLZ Output Enable to Output Low-Z 0 ____ 0 ____ 0 ____ ns tOHZ Output Enable to Output High-Z 1 4 1 4.5 1 5 ns tCD2 Clock to Data Valid (Pipelined) ____ 4.2 ____ 5 ____ 6ns tDC Data Output Hold After Clock High 1 ____ 1 ____ 1 ____ ns tCKHZ Clock High to Output High-Z 1 3 1 4.5 1.5 6 ns tCKLZ Clock High to Output Low-Z 1 ____ 1 ____ 1 ____ ns Port-to-Port Delay tCO Clock-to-Clock Offset 6 ____ 8 ____ 10 ____ ns 4831 tbl 11 |
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