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IDT70V3569S4BFI Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT70V3569S4BFI Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 16 page ©2001 Integrated Device Technology, Inc. APRIL 2001 DSC 4831/8 1 Functional Block Diagram Features: x True Dual-Port memory cells which allow simultaneous access of the same memory location x High-speed clock to data access – Commercial: 4.2/5/6ns (max.) – Industrial: 5/6ns (max) x Pipelined output mode x Counter enable and reset features x Dual chip enables allow for depth expansion without additional logic x Full synchronous operation on both ports – 7.5ns cycle time, 133MHz operation (9.6 Gbps bandwidth) – Fast 4.2ns clock to data out – 1.8ns setup to clock and 0.7ns hold on all control, data, and address inputs @ 133MHz – Data input, address, byte enable and control registers – Self-timed write allows fast cycle time x Separate byte controls for multiplexed bus and bus matching compatibility x LVTTL- compatible, single 3.3V (±150mV) power supply for core x LVTTL- compatible, selectable 3.3V (±150mV)/2.5V (±125mV) power supply for I/Os and control signals on each port x Industrial temperature range (-40°C to +85°C) is available for selected speeds x Available in a 208-pin Plastic Quad Flatpack (PQFP), 208-ball fine-pitch Ball Grid Array, and 256-pin Ball Grid Array HIGH-SPEED 3.3V 16K x 36 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE IDT70V3569S CNTRSTR Counter/ Address Reg. A13R A0R Counter/ Address Reg. CNTENR ADSR CNTENL ADSL CNTRSTL Dout0-8_L Dout9-17_L Dout18-26_L Dout27-35_L Dout0-8_R Dout9-17_R Dout18-26_R Dout27-35_R B W 0 L B W 1 L B W 2 L B W 3 L B W 3 R B W 2 R B W 1 R B W 0 R I/O0L- I/O35L A13L A0L I/O0R -I/O35R Din_L ADDR_L Din_R ADDR_R OER OEL 4831 tbl 01 BE3L BE2L BE1L BE0L R/WL CE0L BE3R BE2R BE1R BE0R R/WR CE0R CE1R CE1L 16K x 36 MEMORY ARRAY CLKR CLKL , |
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