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IDT70V3319S133PRF Datasheet(PDF) 6 Page - Integrated Device Technology |
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IDT70V3319S133PRF Datasheet(HTML) 6 Page - Integrated Device Technology |
6 / 23 page 6.42 IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges 6 NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. ADS, CNTEN, REPEAT = VIH. 3. OE is an asynchronous input signal. Truth Table I—Read/Write and Enable Control(1,2,3) OE CLK CE0 CE1 UB LB R/W Upper Byte I/O9-17 Lower Byte I/O0-8 MODE X ↑ H XXXX High-Z High-Z Deselected–Power Down X ↑ X L X X X High-Z High-Z Deselected–Power Down X ↑ L H H H X High-Z High-Z Both Bytes Deselected X ↑ LH H L L High-Z DIN Write to Lower Byte Only X ↑ LH LH L DIN High-Z Write to Upper Byte Only X ↑ L H LLL DIN DIN Write to Both Bytes L ↑ LH H L H High-Z DOUT Read Lower Byte Only L ↑ LH LH H DOUT High-Z Read Upper Byte Only L ↑ LH L L H DOUT DOUT Read Both Bytes H ↑ L H L L X High-Z High-Z Outputs Disabled 5623 tbl 02 Truth Table II—Address Counter Control(1,2) NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. Read and write operations are controlled by the appropriate setting of R/W, CE0, CE1, UB, LB and OE. 3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the date out will be delayed by one cycle. 4. ADS and REPEAT are independent of all other memory control signals including CE0, CE1 and UB, LB. 5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, UB, LB. 6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location. External Address Previous Internal Address Internal Address Used CLK ADS CNTEN REPEAT(6) I/O(3) MODE XX An ↑ XX L(4) DI/O(0) Counter Reset to last valid ADS load An X An ↑ L(4) XH DI/O (n) External Address Used An Ap Ap ↑ HH H DI/O(p) External Address Blocked—Counter disabled (Ap reused) XAp Ap + 1 ↑ H L(5) HDI/O(p+1) Counter Enabled—Internal Address generation 5623 tbl 03 |
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