8 / 33 page  CY7C1371C CY7C1373C Document #: 38-05234 Rev. *D Page 8 of 33 DQs 52,53,56,57, 58,59,62,63, 68,69,72,73, 74,75,78,79, 2,3,6,7,8,9, 12,13,18,19, 22,23,24,25, 28,29 K6,L6,M6, N6,K7,L7, N7,P7,E6, F6,G6,H6, D7,E7,G7, H7,D1,E1, G1,H1,E2, F2,G2,H2, K1,L1,N1, P1,K2,L2, M2,N2 M11,L11, K11,J11, J10,K10, L10,M10, D10,E10, F10,G10, D11,E11, F11,G11, D1,E1,F1, G1,D2,E2, F2,G2,J1, K1,L1,M1, J2,K2,L2 M2, I/O- Synchronous Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQP[A:D] are placed in a tri-state condition.The outputs are automatically tri-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. DQP[A:D] 51,80,1,30 P6,D6,D2, P2 N11,C11,C1, N1 I/O- Synchronous Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs. During write sequences, DQP[A:D] is controlled by BW[A:D] correspondingly. MODE 31 R3 R1 Input Strap Pin Mode Input. Selects the burst order of the device. When tied to Gnd selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. VDD 15,41,65,91 J2,C4,J4, R4,J6 D4,D8,E4, E8,F4,F8, G4,G8, H4,H8,J4, J8,K4,K8, L4,L8,M4, M8 Power Supply Power supply inputs to the core of the device. VDDQ 4,11,20,27, 54,61,70,77 A1,F1,J1, M1,U1, A7,F7,J7, M7,U7 C3,C9,D3, D9,E3,E9, F3,F9,G3, G9,J3,J9, K3,K9,L3, L9,M3,M9, N3,N9 I/O Power Supply Power supply for the I/O circuitry. VSS 5,10,17,21, 26,40,55,60, 67,71,76,90 D3,E3,F3, H3,K3, M3,N3, P3,D5,E5, F5,H5,K5, M5,N5,P5 C4,C5,C6, C7,C8,D5, D6,D7,E5, E6,E7,F5, F6,F7,G5, G6,G7,H5, H6,H7,J5, J6,J7,K5,K6, K7,L5,L6,L7, M5,M6,M7, N4,N8 Ground Ground for the device. TDO - U5 P7 JTAG serial output Synchronous Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is not being utilized, this pin should be left unconnected. This pin is not available on TQFP packages. TDI - U3 P5 JTAG serial input Synchronous Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being utilized, this pin can be left floating or connected to VDD through a pull up resistor. This pin is not available on TQFP packages. TMS - U2 R5 JTAG serial input Synchronous Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being utilized, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. CY7C1371C–Pin Definitions (continued) Name TQFP BGA fBGA I/O Description |
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