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CY9C62256-70PC Datasheet(PDF) 5 Page - Cypress Semiconductor

Part # CY9C62256-70PC
Description  32K x 8 Magnetic Nonvolatile CMOS RAM
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY9C62256-70PC Datasheet(HTML) 5 Page - Cypress Semiconductor

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PRELIMINARY
CY9C62256
Document #: 38-15001 Rev. *E
Page 5 of 11
AC Test Loads and Waveforms
Switching Characteristics Over the Operating Range[7]
Parameter
Description
CY9C62256-70
Unit
Min.
Max.
Read Cycle
tRC
Read Cycle Time
70
ns
tAA
Address to Data Valid
70
ns
tOHA
Data Hold from Address Change
5
ns
tACE
CE LOW to Data Valid
70
ns
tDOE
OE LOW to Data Valid
35
ns
tLZOE
OE LOW to Low Z[8]
5ns
tHZOE
OE HIGH to High Z[8,9]
25
ns
tLZCE
CE LOW to Low Z[8]
5ns
tHZCE
CE HIGH to High Z[8,9]
25
ns
tPU
CE LOW to Power-up
0
ns
tPD
CE HIGH to Power-down
70
ns
Write Cycle[10,11]
tWC
Write Cycle Time
70
ns
tSCE
CE LOW to Write End
60
ns
tAW
Address Set-up to Write End
60
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Set-up to Write Start
0
ns
tPWE
WE Pulse Width
50
ns
tSD
Data Set-up to Write End
30
ns
tHD
Data Hold from Write End
0
ns
tHZWE
WE LOW to High Z[8, 9]
25
ns
tLZWE
WE HIGH to Low Z[8]
5ns
Notes:
7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 100-pF load capacitance.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
9. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
11. The minimum write pulse width for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
3.0V
5V
OUTPUT
R1 1800
R2
990
100 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
<5 ns
<5 ns
5V
OUTPUT
R1 1800 Ω
R2
990
5pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
1.77V
Equivalent to:
THEVENIN EQUIVALENT
ALL INPUT PULSES
639


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