CY2213
Document #: 38-07263 Rev. *E
Page 5 of 10
State Transition Characteristics
Specifies the maximum settling time of the CLK and CLKB
outputs from device power-up. For VDD and VDDX any
sequences are allowed to power-up and power-down the
CY2213.
From
To
Transition Latency
Description
VDD/VDDX On CLK/CLKB Normal
3 ms
Time from VDD/VDDX is applied and settled to CLK/CLKB outputs settled.
AC Device Characteristics
Parameter
Description
Min.
Max.
Unit
tCYCLE
Clock cycle time
2.50 (400 MHz)
8.00 (125 MHz)
ns
tJCRMS
Cycle-to-cycle RMS jitter
0.25%
% tCYCLE
At 125-MHz frequency
20
ps
At 400-/500-MHz frequency
6.25/5
ps
tJCPK
Cycle-to-cycle jitter (pk-pk)
1.75%
% tCYCLE
At 125-MHz frequency
140
ps
At 200-MHz frequency, XF = 25 MHz
55
ps
At 400-/500-MHz frequency
43.75/35
ps
tJPRMS
Period jitter RMS
0.25%
% tCYCLE
At 125-MHz frequency
20
ps
At 400-/500-MHz frequency
6.25/5
ps
tJPPK
Period jitter (pk-pk)
2.0%
% tCYCLE
At 125-MHz frequency
160
ps
At 200-MHz frequency, XF = 25 MHz
65
ps
At 400-/500-MHz frequency
50/40
ps
tJLT
Long term RMS Jitter (P < 20)
1.75%
% tCYCLE
At 125-MHz frequency
140
ps
At 400-/500-MHz frequency
43.75/35
ps
tJLT
Long term RMS Jitter (20 < P < 40)
2.5%
% tCYCLE
At 125-MHz frequency
200
ps
At 400-/500-MHz frequency
62.5/50
ps
tJLT
Long-term RMS Jitter (40 < P < 60)
3.5%
% tCYCLE
At 125-MHz frequency
280
ps
At 400-/500-MHz frequency
87.5/70
ps
Phase Noise
Phase Noise at 10 kHz (x8 mode) @ 125 MHz
–107
–92
dBc
DC
Long-term average output duty cycle
45
55
%
tDC,ERR
Cycle-cycle duty cycle error at x8 with
15.625-MHz input
70
ps
tCR, tCF
Output rise and fall times (measured at 20% –
80% of VOHmin and VOLmax)
100
400
ps
BWLOOP
PLL Loop Bandwidth
50 kHz (–3 dB)
8 MHz (–20 dB)
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