1M x 4 Static RAM
CY7C1046CV33
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05003 Rev. *A
Revised September 13, 2002
Features
• High speed
—tAA = 10ns
• Low active power for 10 ns speed
— 324 mW (max.)
• 2.0V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
Functional Description[1]
The CY7C1046CV33 is a high-performance CMOS static
RAM organized as 1,048,576 words by 4 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and three-state drivers.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the four I/O
pins (I/O0 through I/O3) is then written into the location
specified on the address pins (A0 through A19).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The four input/output pins (I/O0 through I/O3) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a Write
operation (CE LOW, and WE LOW).
The CY7C1046CV33 is available in a standard 400-mil-wide
32-pin SOJ package with center power and ground (revolu-
tionary) pinout.
Logic Block Diagram
Pin Configuration
A1
A2
A3
A4
A5
A6
A7
A8
COLUMN
DECODER
INPUT BUFFER
POWER
DOWN
WE
OE
I/O0
I/O1
1M x 4
ARRAY
I/O3
I/O2
A0
CE
1
2
3
4
5
6
7
8
9
10
12
21
22
25
24
23
28
27
26
Top View
SOJ
11
29
32
31
30
14
13
19
20
GND
A1
A2
A3
A4
A5
A6
A7
A8
WE
VCC
A18
A15
A12
A14
I/O2
A9
A0
I/O0
I/O1
OE
A17
A16
A13
CE
A9
16
15
17
18
GND
I/O3
VCC
A10
A11
A19
NC
A10
Selection Guide
-8[2]
-10
-12
-15
Unit
Maximum Access Time
810
12
15
ns
Maximum Operating Current
100
90
85
80
mA
Maximum CMOS Standby Current
10
10
10
10
mA
Notes:
1.
For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
2.
Shaded areas contain advance information.
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