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AT87C5111-3ZSIL Datasheet(PDF) 10 Page - ATMEL Corporation |
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AT87C5111-3ZSIL Datasheet(HTML) 10 Page - ATMEL Corporation |
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10 / 86 page  10 AT8xC5111 4190A–8051–11/02 Timer 0: Clock Inputs The SCLKT0 bit in OSCCON register allows to select Timer 0 Subsidiary clock. This allows to perform a Real-Time Clock function. SCLKT0 = 0: Timer 0 uses the standard T0 pin as clock input (Standard mode). SCLKT0 = 1: Timer 0 uses the special Sub Clock as clock input. When the subclock input is selected for Timer 0 and the crystal oscillator is selected for CPU and peripherals, the CKRL prescaler must be set to FF (division factor 2) in order to assure a proper count on Timer 0. With an external a 32 kHz oscillator, the timer interrupt can be set from 1/256 to 256 seconds to perform a Real-Time Clock (RTC) function. The power consumption will be very low as the CPU is in idle mode at 32 kHz most of the time. When more CPU power is needed, the internal RC oscillator is activated and used by the CPU and the others peripherals. Registers Clock Control Register The clock control register is used to define the clock system behavior. Table 2. OSCCON - Clock Control Register (8Fh) SCLKT0 1 0 CkIdle : 6 T0 pin Sub Clock C/T 1 0 OSCCON TMOD Gate INT0 TR0 Timer 0 Control 765 43210 ----- SCLKT0 OSCBEN OSCAEN Bit Number Bit Mnemonic Description 7- Reserved The value read from this bit is indeterminate. Do not set this bit. 6- Reserved The value read from this bit is indeterminate. Do not set this bit. 5- Reserved The value read from this bit is indeterminate. Do not set this bit. 4- Reserved The value read from this bit is indeterminate. Do not set this bit. 3- Reserved The value read from this bit is indeterminate. Do not set this bit. |
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