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AHA4011C-040PJC Datasheet(PDF) 7 Page - List of Unclassifed Manufacturers |
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AHA4011C-040PJC Datasheet(HTML) 7 Page - List of Unclassifed Manufacturers |
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7 / 28 page  PS4011C-0200 Page 3 of 24 Advanced Hardware Architectures, Inc. The use of internal buffers is restricted per the rules defined in Section 2.9 Data Rates and Latencies. Maximum delay required for each block of a given length to pass through the device is fixed, and does not vary with the location or the number of errors received. This delay (or latency), expressed in the number of clocks is discussed in a later section. 2.2 CORRECTING CAPABILITY AND POLYNOMIALS Compared with other codes, RS codes require relatively few “overhead” check bytes to be added to the data stream to achieve a high degree of error detection and correction. Since the AHA4011C deals with bytes (or symbols) rather than with individual bits, when a byte is in error it does not matter how many bits within the byte are corrupted; it is counted as one error. The Reed-Solomon code is defined over the finite field GF(28). The field defining primitive polynomial is: P(x) = x8 + x7 + x2 + x + 1 and the generator polynomial, dependent on the variable R, is given by: where R ∈ {2, 3, 4, 5,. . . 20} for the AHA4011C. This polynomial is specified in international standards, Intelsat IESS 308; RTCA DO-217 Appendix F (Rev D) and the proposed CCITT SG-18. For every 2 check bytes, the decoder corrects either 2 erasures or 1 error. An erasure can be determined with a parity detector or a signal dropout detector external to the chip. An erasure is indicated by the ERASE signal when the erased byte is clocked in the device. Correcting “erasures” takes only half as much of the correction capability of the RS code as it takes to correct “errors”, since the position information is already known for “erasures”. The correction ability of the code is bounded as: R ≥ # erasures + 2(# errors) Valid block length (N) is defined by the relationship: R + 1 ≤ N ≤ 255 where R ranges from 2 to 20. A complete codeword can therefore range from a minimum of 3 bytes to a maximum of 255 bytes. For further discussion on error rate performance, refer to Section 2.1 Reed-Solomon (ECC) Module and Error Rate Performance. Figure 1: Block Diagram A typical system block diagram is shown in the following figure. Figure 2: Typical Applications Diagram Gx () x αi – () i 120 = 119 R + ∏ = DI INPUT BUFFER ECC CORE CONTROL DO 367x9 OUTPUT BUFFER 256x9 REGISTER RDYON RSTN DSIN DSON GND VDD CRTN RDYIN CLK RDYIN REGISTER ERASE DI[7:0] CLK RSTN DSIN DSON RDYON CRTN DO[7:0] ERR VDD GND DATA SOURCE AHA4011C ECC COPROCESSOR CHANNEL 1 TO x BITS WIDE AHA4011C ECC COPROCESSOR DATA SINK SYSTEM CONTROLLER SYSTEM CONTROLLER A 8 8 8 8 B C ENCODER COMMUNICATIONS DECODER BLOCK FORMAT AT: KDATA PLUS R “DUMMY” BYTES KDATA PLUS R CHECK BYTES KDATA BYTES A B C |
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