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AD7920 Datasheet(PDF) 4 Page - Analog Devices |
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AD7920 Datasheet(HTML) 4 Page - Analog Devices |
4 / 20 page REV. B –4– AD7910/AD7920 AD7910/AD7920 Parameter Limit at TMIN, TMAX Unit Description fSCLK 2 10 kHz min 3 5 MHz max tCONVERT 14 tSCLK AD7910 16 tSCLK AD7920 tQUIET 50 ns minMinimum Quiet Time Required between Bus Relinquish and Start of Next Conversion t1 10 ns min Minimum CS Pulse Width t2 10 ns min CS to SCLK Setup Time t3 4 22 ns max Delay from CS until SDATA Three-State Disabled t4 4 40 ns max Data Access Time after SCLK Falling Edge t5 0.4 tSCLK ns min SCLK Low Pulse Width t6 0.4 tSCLK ns min SCLK High Pulse Width t7 5 SCLK to Data Valid Hold Time 10 ns min VDD £ 3.3 V 9.5 ns min 3.3 V < VDD £ 3.6 V 7 ns min VDD > 3.6 V t8 6 36 ns max SCLK Falling Edge to SDATA Three-State See Note 7 ns min SCLK Falling Edge to SDATA Three-State tPOWER-UP 8 1 ms max Power-Up Time from Full Power-Down NOTES 1Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V. 2Mark/Space ratio for the SCLK input is 40/60 to 60/40. 3Minimum f SCLK at which specifications are guaranteed. 4Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 1.8 V when V DD = 2.35 V and 0.8 V or 2.0 V for VDD > 2.35 V. 5Measured with a 50 pF load capacitor. 6t 8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the Timing Characteristics is the true bus relinquish time of the part and is independent of the bus loading. 7t 7 values apply to t8 minimum values also. 8See Power-Up Time section. Specifications subject to change without notice. AD7920–SPECIFICATIONS1 (continued) Parameter A Grade 1, 2 B Grade 1, 2 Unit Test Conditions/Comments POWER REQUIREMENTS VDD 2.35/5.25 2.35/5.25 V min/max IDD Digital I/Ps = 0 V or VDD Normal Mode (Static) 2.5 2.5 mA typ VDD = 4.75 V to 5.25 V, SCLK On or Off 1.2 1.2 mA typ VDD = 2.35 V to 3.6 V, SCLK On or Off Normal Mode (Operational) 3 3 mA max VDD = 4.75 V to 5.25 V, fSAMPLE = 250 kSPS 1.4 1.4 mA max VDD = 2.35 V to 3.6 V, fSAMPLE = 250 kSPS Full Power-Down Mode 1 1 mA max Typically 50 nA Power Dissipation 7 Normal Mode (Operational) 15 15 mW max VDD = 5 V, fSAMPLE = 250 kSPS 4.2 4.2 mW max VDD = 3 V, fSAMPLE = 250 kSPS Full Power-Down 5 5 mW max VDD = 5 V 33 mW max VDD = 3 V NOTES 1Temperature range from –40 ∞C to +85∞C. 2Operational from V DD = 2.0 V, with input low voltage (VINL) 0.35 V max. 3See Terminology section. 4B Grade, maximum specs apply as typical figures when V DD = 4.75 V to 5.25 V. 5SC70 values guaranteed by characterization. 6Guaranteed by characterization. 7See Power vs. Throughput Rate section. Specifications subject to change without notice. TIMING SPECIFICATIONS1 (V DD = 2.35 V to 5.25 V, TA = TMIN to TMAX, unless otherwise noted.) |
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