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AD9642BCPZ-250 Datasheet(PDF) 8 Page - Analog Devices

Part # AD9642BCPZ-250
Description  1.8 V Analog-to-Digital Converter (ADC)
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9642BCPZ-250 Datasheet(HTML) 8 Page - Analog Devices

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Data Sheet
AD9642
Rev. B | Page 7 of 28
TIMING SPECIFICATIONS
Table 5.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
SPI TIMING REQUIREMENTS
See Figure 58 for SPI timing diagram
tDS
Setup time between the data and the rising edge of SCLK
2
ns
tDH
Hold time between the data and the rising edge of SCLK
2
ns
tCLK
Period of the SCLK
40
ns
tS
Setup time between CSB and SCLK
2
ns
tH
Hold time between CSB and SCLK
2
ns
tHIGH
Minimum period that SCLK should be in a logic high state
10
ns
tLOW
Minimum period that SCLK should be in a logic low state
10
ns
tEN_SDIO
Time required for the SDIO pin to switch from an input to an output
relative to the SCLK falling edge (not shown in Figure 58)
10
ns
tDIS_SDIO
Time required for the SDIO pin to switch from an output to an input
relative to the SCLK rising edge (not shown in Figure 58)
10
ns


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