TMS44100, TMS44100P, TMS46100, TMS46100P

4194304-WORD BY 1-BIT

DYNAMIC RANDOM-ACCESS MEMORIES

SMHS561A – MARCH 1995 – REVISED JUNE 1995

10

POST OFFICE BOX 1443

timing requirements over recommended ranges of supply voltage and operating free-air

temperature (continued)

’4x100 - 60

’4x100P - 60

’4x100 - 70

’4x100P - 70

’4x100 - 80

’4x100P - 80

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

tCSR

Delay time, CAS low to RAS low (CBR refresh only)

5

5

5

ns

tCHS

Hold time, CAS low after RAS high, self refresh

–50

–50

–50

ns

tCWD

Delay time, CAS low to W low (read-write operation only)

15

18

20

ns

tRAD

Delay time, RAS low to column address (see Note 15)

15

30

15

35

15

40

ns

tRAL

Delay time, column address to RAS high

30

35

40

ns

tCAL

Delay time, column address to CAS high

30

35

40

ns

tRCD

Delay time, RAS low to CAS low (see Note 15)

20

45

20

52

20

60

ns

tRPC

Delay time, RAS high to CAS low

0

0

0

ns

tRSH

Delay time, CAS low to RAS high

15

18

20

ns

tRWD

Delay time, RAS low to W low (read-write operation only)

60

70

80

ns

tTAA

Access time from address (test mode)

35

40

45

ns

tTCPA

Access time from column precharge (test mode)

40

45

50

ns

tTRAC

Access time from RAS (test mode)

65

75

85

ns

tREF

Refresh time interval

’4x100

16

16

16

ms

tREF

Refresh time interval

’4x100P

128

128

128

ms

tT

Transition time

2

50

2

50

2

50

ns

NOTE 15: The maximum value is specified only to assure access time.

PARAMETER MEASUREMENT INFORMATION

1.31 V

VCC = 5 V

CL = 100 pF

Output Under Test

Output Under Test

CL = 100 pF

(b) ALTERNATE LOAD CIRCUIT

(a) LOAD CIRCUIT

RL = 218 Ω

R1 = 828

Ω

R2 = 295

Ω

Figure 1. Load Circuits for Timing Parameters