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PC107AVZFU100LD Datasheet(PDF) 9 Page - ATMEL Corporation |
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PC107AVZFU100LD Datasheet(HTML) 9 Page - ATMEL Corporation |
9 / 50 page 9 PC107A [Preliminary] 2137C–HIREL–03/04 Notes: 1. This pin has an internal pull-up resistor which is enabled only when the PC107A is in the reset state. The value of the inter- nal pull-up resistor is not guaranteed, but is sufficient to ensure that a logic "1" is read into configuration bits during reset. 2. This pin is a reset configuration pin. 3. MDL[0] is a reset configuration pin and has an internal pull-up resistor which is enabled only when the MPC107 is in the reset state.The value of the internal pull-up resistor is not guaranteed, but is sufficient to insure that a logic '1' is read into configuration bits during reset. 4. Multi-pin signals such as AD[0–31] or DL[0–31] have their physical package pin numbers listed in order corresponding to the signal names. Ex: AD0 is on pin D21, AD1 is on pin D23,... AD31 is on pin N23. 5. SDMA[10–1] are reset configuration pins and have internal pull-up resistors which are enabled only when the MPC107 is in the reset state.The values of the internal pull-up resistors is not guaranteed, but are sufficient to ensure that logic "1"s are read into the configuration bits during reset. 6. Recommend a weak pull-up resistor (2 k Ω– 10 kΩ) be placed on this PCI control pin to LV DD. 7. VIH and VIL for these signals are the same as the PCI VIH and VIL entries in Table 7, “DC Electrical Specifications.” 8. Recommend a weak pull-up resistor (2 k Ω – 10 kΩ) be placed on this pin to OV DD. 9. Recommend a weak pull-up resistor (2 k Ω – 10 kΩ) be placed on this pin to GV DD. 10. This pin has an internal pull-up resistor; the value of the internal pull-up resistor is not guaranteed, but is sufficient to prevent unused inputs from floating. 11. This pin is affected by programmable PCI_HOLD_DEL parameter, see “PCI Signal Output Hold Timing” on page 29.” 12. This pin is an open drain signal. 13. This pin is a sustained tri-state pin as defined by the PCI Local Bus Specification. 14. See “Connection Recommendations” on page 43 for additional information on this pin. 15. A weak pull-up resistor is recommend (2 k Ω – 10 kΩ) to be placed on this pin to BV DD. 16. If BV DD = 2.5V ±5%, this microprocessor interface pin needs to be DC voltage level shifted from OVDD (3.3 ±0.3V) to 2.5V ±5%; this can typically be accomplished with a two resistor voltage divider circuit since the signal is an output only signal. |
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