Electronic Components Datasheet Search |
|
AD9652 Datasheet(PDF) 6 Page - Analog Devices |
|
AD9652 Datasheet(HTML) 6 Page - Analog Devices |
6 / 37 page Data Sheet AD9652 Rev. B | Page 5 of 36 VREF = 1 V VREF = 1.25 V, Default Parameter1 Temperature Min Typ Max Min Typ Max Unit WORST OTHER (NOT INCLUDING 2nd or 3rd HARMONIC) fIN = 30 MHz (Use Nyquist 1 Settings) 25°C −101 −102 dBc fIN = 70 MHz (Use Nyquist 1 Settings) 25°C −99 −98 −90 dBc Full −86 dBc fIN = 70 MHz (Use Nyquist 1 Settings, with Dither Enabled) 25°C −100 −100 dBc fIN = 170 MHz (Use Nyquist 2 Settings) 25°C −91 −90 dBc fIN = 170 MHz (Use Nyquist 2 Settings, with Dither Enabled) 25°C −90 −95 dBc fIN = 305 MHz (Use Nyquist 2 Settings) 25°C −98 −97 dBc fIN = 400 MHz (Use Nyquist 3 Settings) 25°C −92 −91 dBc TWO-TONE SFDR fIN = 70.1 MHz (−7 dBFS ), 72.1 MHz (−7 dBFS ) 25°C 93 dBc fIN = 184.12 MHz (−7 dBFS ), 187.12 MHz (−7 dBFS ) 25°C 83 dBc CROSSTALK2 Full 90 90 dB FULL POWER BANDWIDTH3 25°C 485 485 MHz NOISE BANDWIDTH4 25°C 650 650 MHz 1 See the AN-835 Application Note,UnderstandingHighSpeed ADC Testing and Evaluation, for a complete set of definitions. 2 Crosstalk is measured at 100 MHz with −1.0dBFS on one channel and no input on the alternate channel. 3 Full power bandwidth is the bandwidth of operation in which proper ADC performance can be achieved. 4 Noise bandwidth is the −3 dB bandwidth for the ADC inputs across which noise can enter the ADCand is not attenuated internally. DIGITAL SPECIFICATIONS AVDD3 = 3.3 V, AVDD = AVDD_CLK = 1.8 V, SPIVDD = DRVDD = 1.8 V, sample rate = 310 MSPS (clock input = 1240 MHz, AD9652 divided by 4), VIN = −1.0 dBFS differential input, 2.5 V p-p full-scale input range, DCS enabled, dither disabled, unless otherwise noted. Table 3. Parameter Test Conditions/Comments Temperature Min Typ Max Unit DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL Differential Input Voltage Full 0.3 3.6 V p- p Input Voltage Range Full AGND AVDD_CLK V Internal Common-Mode Bias Full 0.9 V Input Common-Mode Range Full 0.9 1.4 V High Level Input Current Full +10 +145 µA Low Level Input Current Full −155 −15 µA Input Capacitance1 Full 5 pF Input Resistance1 Full 10 kΩ SYNC INPUT Logic Compliance CMOS/LVDS Internal Bias Full 0.9 V Input Voltage Range Full AGND AVDD_CLK V High Level Input Voltage Full 1.2 AVDD_CLK V Low Level Input Voltage Full AGND 0.6 V High Level Input Current Full −15 +110 µA Low Level Input Current Full −105 +15 µA Input Capacitance Full 1.5 pF Input Resistance Full 16 kΩ |
Similar Part No. - AD9652 |
|
Similar Description - AD9652 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |