FEBRUARY 2005

DSC-5280/08

1

©2005 Integrated Device Technology, Inc.

Features

x

128K x 36, 256K x 18 memory configurations

x

x

x

x

x

Supports fast access times:

Commercial:

– 7.5ns up to 117MHz clock frequency

Commercial and Industrial:

– 8.0ns up to 100MHz clock frequency

– 8.5ns up to 87MHz clock frequency

x

LBO

LBO

LBO

LBO

LBO input selects interleaved or linear burst mode

x

x

x

x

x

Self-timed write cycle with global write control (

GW

GW

GW

GW

GW), byte write

enable (

BWE

BWE

BWE

BWE

BWE), and byte writes (BW

BW

BW

BW

BWx)

x

x

x

x

x

3.3V core power supply

x

x

x

x

x

Power down controlled by ZZ input

x

x

x

x

x

3.3V I/O

x

x

x

x

x

Optional - Boundary Scan JTAG Interface (IEEE 1149.1

compliant)

x

x

x

x

x

Packaged in a JEDEC Standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball

grid array

Pin Description Summary

NOTE:

1.

Description

The IDT71V3577/79 are high-speed SRAMs organized as

128K x 36/256K x 18. The IDT71V3577/79 SRAMs contain write, data,

address and control registers. There are no registers in the data output

path (flow-through architecture). Internal logic allows the SRAM to gen-

erate a self-timed write based upon a decision which can be left until the

end of the write cycle.

The burst mode feature offers the highest level of performance to the

system designer, as the IDT71V3577/79 can provide four cycles of data

for a single address presented to the SRAM. An internal burst address

counter accepts the first cycle address from the processor, initiating the

access sequence. The first cycle of output data will flow-through from the

array after a clock-to-data access time delay from the rising clock edge of

the same cycle. If burst mode operation is selected (

ADV=LOW), the

subsequent three cycles of output data will be available to the user on the

next three rising clock edges. The order of these three addresses are

defined by the internal burst counter and the

LBO input pin.

The IDT71V3577/79 SRAMs utilize IDT’s latest high-performance

CMOS process and are packaged in a JEDEC standard 14mm x 20mm

100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array

(BGA) and a 165 fine pitch ball grid array (fBGA).

Address Inputs

Input

Synchronous

CE

Chip Enable

Input

Synchronous

Chip Selects

Input

Synchronous

OE

Output Enable

Input

Asynchronous

GW

Global Write Enable

Input

Synchronous

BWE

Byte Write Enable

Input

Synchronous

Individual Byte Write Selects

Input

Synchronous

CLK

Clock

Input

N/A

ADV

Burst Address Advance

Input

Synchronous

ADSC

Address Status (Cache Controller)

Input

Synchronous

ADSP

Address Status (Processor)

Input

Synchronous

LBO

Linear / Interleaved Burst Order

Input

DC

TMS

Test Mode Select

Input

Synchronous

TDI

Test Data Input

Input

Synchronous

TCK

Test Clock

Input

N/A

TDO

Test Data Output

Output

Synchronous

TRST

JTAG Reset (Optional)

Input

Asynchronous

ZZ

Sleep Mode

Input

Asynchronous

Data Input / Output

I/O

Synchronous

Core Power, I/O Power

Supply

N/A

Ground

Supply

N/A

5280 tbl 01

128K X 36, 256K X 18

3.3V Synchronous SRAMs

3.3V I/O, Flow-Through Outputs

Burst Counter, Single Cycle Deselect

IDT71V3577S

IDT71V3579S

IDT71V3577SA

IDT71V3579SA