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LTC3901EGN Datasheet(PDF) 10 Page - Linear Technology |
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LTC3901EGN Datasheet(HTML) 10 Page - Linear Technology |
10 / 16 page LTC3901 10 3901f APPLICATIO S I FOR ATIO the resistors to the LTC3901 CSX+/CSX– pins as short as possible . Add a series resistor, RCSX3, with value equal to parallel sum of RCSX1 and RCSX2 to the CSX– pin and connect the other end of RCSX3 directly to the source of the MOSFET. SYNC Input Figure 8 shows the external circuit for the LTC3901 SYNC input. The gate drive transformer (T2) should be selected based on the primary switching frequency and SDRA/ SDRB output voltage. The values of the CSG and RSYNC should then be adjusted to obtain a optimum SYNC pulse shape and amplitude. The amplitude of the SYNC pulse should be much higher than the LTC3901 SYNC threshold of ±1.4V. Amplitudes greater than ±5V will help to speed up the SYNC comparator and reduce the propagation delay from SYNC to the drivers. When SDRA and SDRB lines go low, the resulting under- shoot or overshoot must not exceed the minimum SYNC threshold of ±1V. higher than 4.5V. This reduces the number of external components needed. The LTC3901 has an UVLO detector that pulls the drivers’ output low if VCC < 4.1V. The output remains off from VCC = 1V to 4.1V. The UVLO detector has 0.5V of hyster- esis to prevent chattering. In a typical push-pull converter, the secondary side cir- cuits have no power until the primary side controller starts operating. Since power for the LTC3901 is derived from the power transformer T1, the LTC3901 will initially re- main off. During this period (VCC < 4.1V), the synchronous MOSFETs ME and MF will remain off and the MOSFETs’ body diodes will conduct. The MOSFETs may experience very high power dissipation due to a high voltage drop in the body diodes. To prevent MOSFET damage, a VCC voltage greater than 4.1V should be provided quickly. The VCC supply circuit in Figure 9 will provide power for the LTC3901 within the first few switching pulses of the primary controller, preventing overheating of the MOSFETs. Full-Bridge Converter Application The LTC3901 can be used in full-bridge converter applica- tions. Figure 10 shows a simplified full-bridge converter circuit. The LTC3901 circuit and operation is the same as in the push-pull application (refer to Figure 1). On the pri- mary side there are four power MOSFETs, MA to MD, driven by the respective outputs of the primary controller. Trans- former T3 and T4 step up the gate drives for MA and MC. Each full cycle of the full-bridge converter includes four distinct periods which are similar to those found in the push-pull application. Figure 11 shows the full-bridge converter switching waveforms. The shaded areas corre- spond to power delivery periods. Figure 9. VCC/PVCC Regulator Figure 8. SYNC Input Circuit T2 CSG 0.1µF PRIMARY CONTROLLER LTC3901 SYNC 3901 F08 SDRA SDRB RSG 220Ω RSYNC 4.7k VCC/PVCC Regulator The VCC/PVCC supply for the LTC3901 can be generated by peak rectifying the transformer secondary winding as shown in Figure 9. The Zener diode DZ sets the output voltage (VZ – 0.7V). Resistor RB (on the order of a few hundred ohms), in series with the base of QREG, may be required to surpress high frequency oscillations depend- ing on QREG’s selection. A power MOSFET can also be used by increasing the zener diode value to offset the drop of the gate-to-source voltage. The VCC input is separated from the PVCC input through a 100Ω resistor. This lowers the driver switching feedthrough. Connect a 1µF bypass ca- pacitor for the VCC supply. PVCC supply current varies linearly with the supply voltage, driver load and clock frequency. A 4.7µF bypass capacitor for the PVCC supply is sufficient for most applications. Alternatively, the LTC3901 can be powered directly by VOUT if the voltage is 3901 F09 D3 MBR0540 T1 SECONDARY WINDING 0.1µF RZ 2k RB OPTIONAL QREG FZT690B CPVCC 4.7µF CVCC 1µF PVCC VCC 6V DZ RVCC 100Ω |
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