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IDT723646L12PF Datasheet(PDF) 3 Page - Integrated Device Technology |
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IDT723646L12PF Datasheet(HTML) 3 Page - Integrated Device Technology |
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3 / 35 page  3 IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™ WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE bidirectional interface between microprocessors and/or buses with synchro- nous control. CommunicationbetweeneachportmaybypasstheFIFOsviatwomailbox registers. The mailbox registers' width matches the selected bus width of ports B and C. Each mailbox register has a flag ( MBF1 and MBF2) to signal when new mail has been stored. TwokindsofresetareavailableontheseFIFOs:MasterResetandPartial Reset. Master Reset initializes the read and write pointers to the first location ofthememoryarrayandselectsserialflagprogramming,parallelflagprogram- ming,or oneofthreepossibledefaultflagoffsetsettings,8,16or64. EachFIFO has its own, independent Master Reset pin, MRS1 and MRS2. PartialResetalsosetsthereadandwritepointerstothefirstlocationofthe memory. Unlike Master Reset, any settings existing prior to Partial Reset (i.e., programmingmethodandpartialflagdefaultoffsets)areretained. PartialReset is useful since it permits flushing of the FIFO memory without changing any configuration settings. Each FIFO has its own, independent Partial Reset pin, PRS1 and PRS2. These devices have two modes of operation: In the IDT Standard mode, the first word written to an empty FIFO is deposited into the memory array. A read operation is required to access that word (along with all other words residing in memory). In the First Word Fall Through mode (FWFT), the first word written to an empty FIFO appears automatically on the outputs, no read operation required (Nevertheless, accessing subsequent words does necessitate a formal read request). The state of the BE/ FWFTpin during Master Reset determines the mode in use. Each FIFO has a combined Empty/Output Ready Flag ( EFA/ORA and EFB/ORB) and a combined Full/Input Ready Flag (FFA/IRA and FFC/IRC). The EF and FFfunctions are selected in the IDT Standard mode. EF indicates whether or not the FIFO memory is empty. FF shows whether the memory is full or not. The IR and OR functions are selected in the First Word Fall Through mode. IR indicates whether or not the FIFO has available memory locations. OR shows whether the FIFO has data available for reading or not. It marks the presence of valid data on the outputs. Each FIFO has a programmable Almost-Empty flag ( AEAandAEB)and aprogrammableAlmost-Fullflag( AFAandAFC).AEAandAEBindicatewhen aselectednumberofwordsremainintheFIFOmemory. AFAandAFCindicate when the FIFO contains more than a selected number of words. FFA/IRA,FFC/IRC,AFAandAFCaretwo-stagesynchronizedtothePort Clock that writes data into its array. EFA/ORA,EFB/ORB,AEA, andAEB are two-stage synchronized to the Port Clock that reads data from its array. Programmableoffsetsfor AEA,AEB,AFA,AFCareloadedinparallelusingPort A or in serial via the SD input. The Serial Programming Mode pin ( SPM)makes thisselection.Threedefaultoffsetsettingsarealsoprovided.The AEAandAEB threshold can be set at 8, 16 or 64 locations from the empty boundary and the AFAandAFCthresholdcanbesetat8,16or64locationsfromthefullboundary. AllthesechoicesaremadeusingtheFS0andFS1inputsduringMasterReset. Two or more FIFOs may be used in parallel to create wider data paths. Such a width expansion requires no additional, external components. Further- more, two IDT723626/723636/723646 FIFOs can be combined with unidirec- tionalFIFOscapableofFirstWordFallThroughtiming(i.e.theSuperSyncFIFO family) to form a depth expansion. If, at any time, the FIFO is not actively performing a function, the chip will automatically power down. During the power down state, supply current consumption(ICC)isataminimum.Initiatinganyoperation(byactivatingcontrol inputs) will immediately take the device out of the power down state. The IDT723626/723636/723646s are characterized for operation from 0 °C to 70°C. Industrial temperature range (–40°C to +85°C) is available by special order. They are fabricated using IDT’s high speed, submicron CMOS technology. |
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