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TLV62568DRL Datasheet(PDF) 8 Page - Texas Instruments |
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TLV62568DRL Datasheet(HTML) 8 Page - Texas Instruments |
8 / 26 page 8 TLV62568, TLV62568P SLVSD89A – NOVEMBER 2016 – REVISED APRIL 2017 www.ti.com Product Folder Links: TLV62568 TLV62568P Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated Feature Description (continued) The TLV62568 is able to start into a pre-biased output capacitor. The converter starts with the applied bias voltage and ramps the output voltage to its nominal value. 7.3.4 Switch Current Limit The switch current limit prevents the device from high inductor current and drawing excessive current from a battery or input voltage rail. Excessive current might occur with a heavy load or shorted output circuit condition. The TLV62568 adopts the peak current control by sensing the current of the high-side switch. Once the high-side switch current limit is reached, the high-side switch is turned off and low-side switch is turned on to ramp down the inductor current with an adaptive off-time. 7.3.5 Under Voltage Lockout To avoid mis-operation of the device at low input voltages, under voltage lockout is implemented that shuts down the device at voltages lower than VUVLO with VHYS_UVLO hysteresis. 7.3.6 Thermal Shutdown The device enters thermal shutdown once the junction temperature exceeds the thermal shutdown rising threshold, TJSD. Once the junction temperature falls below the falling threshold, the device returns to normal operation automatically. 7.4 Device Functional Modes 7.4.1 Enabling/Disabling the Device The device is enabled by setting the EN input to a logic High. Accordingly, a logic Low disables the device. If the device is enabled, the internal power stage starts switching and regulates the output voltage to the set point voltage. The EN input must be terminated and should not be left floating. 7.4.2 Power Good The TLV62568P has a power good output. The PG pin goes high impedance once the output is above 95% of the nominal voltage, and is driven low once the output voltage falls below typically 90% of the nominal voltage. The PG pin is an open-drain output and is specified to sink up to 1 mA. The power good output requires a pull-up resistor connecting to any voltage rail less than 5.5 V. The PG signal can be used for sequencing of multiple rails by connecting it to the EN pin of other converters. Leave the PG pin unconnected when not used. Table 1. PG Pin Logic DEVICE CONDITIONS LOGIC STATUS HIGH Z LOW Enable EN = High, VFB ≥ VPG √ EN = High, VFB ≤ VPG √ Shutdown EN = Low √ Thermal Shutdown TJ > TJSD √ UVLO 1.4 V < VIN < VUVLO √ Power Supply Removal VIN ≤ 1.4 V √ |
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