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OPA837IDCKT Datasheet(PDF) 5 Page - Texas Instruments |
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OPA837IDCKT Datasheet(HTML) 5 Page - Texas Instruments |
5 / 51 page 5 OPA837 www.ti.com SBOS673 – SEPTEMBER 2017 Product Folder Links: OPA837 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated (1) Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C, overtemperature limits by characterization and simulation; (B) Not tested in production, limits set by characterization and simulation; (C) Typical value only for information. (2) For a complete selection of TI high speed amplifiers, visit www.ti.com. (3) Input offset voltage drift, input bias current drift, and input offset current drift are average values calculated by taking data at the end points, computing the difference, and dividing by the temperature range. Typical drift specifications are ±1σ. Maximum drift specifications are set by the min, max sample packaged test data using a wafer-level screened drift. Min, max drift is not specified by final automated test equipment (ATE) nor by QA sample testing. (4) Current is considered positive out of the pin. 6.5 Electrical Characteristics: VS = 5 V at VS+ = 5 V, VS– = 0 V, RF = 0 Ω, RL = 2 kΩ, G = 1 V/V, input and output referenced to mid-supply, and TA ≈ 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST LEVEL(1) AC PERFORMANCE SSBW Small-signal bandwidth VOUT = 20 mVPP, G = 1 90 105 MHz C VOUT = 20 mVPP, G = 2 45 C VOUT = 20 mVPP, G = 10 5 C GBP Gain-bandwidth product VOUT = 20 mVPP, G = 10 45 50 MHz C LSBW Large-signal bandwidth VOUT = 2 VPP, G = 2 26 MHz C Bandwidth for 0.1-dB flatness VOUT = 200 mVPP, G = 2 6 MHz C SR Slew rate From LSBW(2) 105 V/µs C tR, tF Rise, fall time VOUT = 0.5-V step, G = 2, input tR = 10ns 10 11 ns C Overshoot VOUT = 2-V step, G = 2, input tR = 40 ns 7.0% C Settling time to 0.1% VOUT = 2.0-V step, G = 1, input tR = 4 ns 25 ns C Settling time to 0.01% VOUT = 2.0-V step, G = 1, input tR = 4 ns 40 ns C HD2 Second-order harmonic distortion f = 100 kHz, VO = 2 VPP, G = 1 (see Figure 73) –120 dBc C HD3 Third-order harmonic distortion f = 100 kHz, VO = 2 VPP, G = 1 (see Figure 73) –145 dBc C Input voltage noise f = 500 Hz 4.7 nV/ √Hz C Voltage noise 1/f corner frequency See Figure 39 35 Hz C Input current noise f = 20 kHz 0.4 pA/ √Hz C Current noise 1/f corner frequency See Figure 39 5 kHz C Overdrive recovery time G = 2, 2x output overdrive (see Figure 30) 75 ns C Closed-loop output impedance f = 1 MHz, G = 1 (see Figure 38) 0.14 Ω C DC PERFORMANCE AOL Open-loop voltage gain VO = ±2 V, RL = 2 kΩ 120 135 dB A Input-referred offset voltage TA ≈ 25°C –130 ±30 130 µV A TA = 0°C to +70°C (DCK package) –170 ±30 200 B TA = –40°C to +85°C (DCK package) –234 ±30 226 B TA = –40°C to +125°C (DCK package) –234 ±30 290 B Input offset voltage drift(3) DCK package, TA = –40°C to +125°C –1.6 ±0.4 1.6 µV/°C B Input offset voltage drift(3) DBV package, TA = –40°C to +125°C –2.0 ±0.4 2.0 µV/°C B Input bias current(4) TA ≈ 25°C 150 340 520 nA A TA = 0°C to +70°C 50 340 664 B TA = –40°C to +85°C 50 340 718 B TA = –40°C to +125°C 50 340 850 B Input bias current drift(3) TA = –40°C to +125°C 0.8 1.5 3.3 nA/°C B Input offset current TA ≈ 25°C –40 ±6 40 nA A TA = 0°C to +70°C –46 ±6 52 B TA = –40°C to +85°C –56 ±6 55 B TA = –40°C to +125°C –56 ±6 65 B Input offset current drift(3) TA = –40°C to +125°C –250 ±40 250 pA/°C B |
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