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CY7C1370CV25
CY7C1372CV25
Document #: 38-05235 Rev. *C
Page 2 of 27
A0, A1, A
C
MODE
BWa
BWb
WE
CE1
CE2
CE3
OE
READ LOGIC
DQs
DQPa
DQPb
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
MEMORY
ARRAY
E
E
INPUT
REGISTER 0
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC
A0'
A1'
D1
D0
Q1
Q0
A0
A1
C
ADV/LD
ADV/LD
E
INPUT
REGISTER 1
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
CLK
CEN
WRITE
DRIVERS
ZZ
Sleep
Control
Logic Block Diagram-CY7C1372CV25 (1M x 18)
Selection Guide
CY7C1370CV25-250
CY7C1372CV25-250
CY7C1370CV25-225
CY7C1372CV25-225
CY7C1370CV25-200
CY7C1372CV25-200
CY7C1370CV25-167
CY7C1372CV25-167 Unit
Maximum Access Time
2.6
2.8
3.0
3.4
ns
Maximum Operating Current
350
325
300
275
mA
Maximum CMOS Standby
Current
70
70
70
70
mA
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.