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5B11N-Rev.F001

EC25C64

64Kbits SPI Serial EEPROM

Pin Configuration

(SOP-8/TSSOP-8)

(DFN-8)

Pin Definition

Pin Descriptions

Chip Select (

)

The CS pin is used to enable or disable the device. Upon power-up, CS must follow the supply voltage. When

the device is ready for instruction input, this signal requires a High-to-Low transition. Once CS is stable at Low,

the device is enabled. Then the master and slave can communicate among each other through SCK, SI, and

SO pins. Upon completion of transmission, CS must be driven to High in order to stop the operation or start

the internal write operation. And the device will enter into standby mode, unless an internal write operation is in

progress. During this mode, SO becomes high impedance.

Serial Clock (SCK)

Under the SPI modes (0,0) and (1,1),this clock signal provides synchronization between the master and

EC25C64.Typically,Op-Codes,addresses and data are latched from SI at the rising edge of SCK, while data

from SO are clocked out at the falling edge of SCK.

Serial Data Input (SI)

Data Input pin.

Serial Data Output(SO)

Data output pin.

Write Protect (

)

This active Low input signal is utilized to initiate Hardware Write Protection mode. This mode prevents the

Block Protection bits and the WPEN bit in the Status Register from being modified. To activate the Hardware

Write Protection, WP must be Low simultaneously when WPEN is set to 1.

Hold (

)

This feature is used to suspend the device in the middle of a serial sequence and temporarily ignore further

communication on the bus (SI,SO,SCK).The HOLD signal transitions must occur only when SCK is Low and be

held stable during SCK transitions. Connecting HOLD to High disables this feature. Figure.8 shows Hold timing.

Pin No.

Pin Name

I/O

Definition

1

CS

I

Chip Select

2

SO

O

Serial Data Output

3

WP

I

Write Protect Input

4

GND

-

Ground

5

SI

I

Serial Data Input

6

SCK

I

Serial Clock

7

HOLD

I

Hold function

8

VCC

-

Supply Voltage