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EC25C64 Datasheet(PDF) 5 Page - E-CMOS Corporation |
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EC25C64 Datasheet(HTML) 5 Page - E-CMOS Corporation |
5 / 16 page E-CMOS Corp. (www.ecmos.com.tw) Page 5 of 16 5B11N-Rev.F001 EC25C64 64Kbits SPI Serial EEPROM Device Operation Status Register The Status Register accessible by the user consists of 8-bits data for write protection control and write status. It Hardware Write Protection is enabled or WEN is set to 0. If neither is true, it can be modified by a valid instruction. becomes Read-Only under any of the following conditions: Table 1: Status Register Note: During internal write cycles, bits 0 to 7 are temporarily 1's. Table 2: Block Protection by BP0 and BP1 Bit Symbol Name Description 0 RDY Ready When RDY = 0, device is ready for an instruction. When RDY = 1, device is busy. As busy, device only accepts Read Status Register command. 1 WEN Write Enable This represents the write protection status of the device. When WEN = 0, Status Register and entire array cannot be modified, regardless the setting of WPEN,WP pin or block protection. Write Enable command (WREN) can be used to set WEN to 1. Upon power-up stage, WEN is reset to 0. 2 BP0 Block Protect Bit Despite of the status on WPEN, WP or WEN, BP0 and BP1 configure any combinations of the four blocks being protected (Table2). They are non-volatile memory and programmed to 0 by factory. 3 BP1 Block Protect Bit 4 X Don’t Care Values can be either 0 or 1, but are not retained. Mostly always 0, except during write operation. 5 X Don’t Care 6 X Don’t Care 7 WPEN Write Protect Enable This bit can be utilized to enable Hardware Write Protection, together with WP pin. If enabled, Status Register becomes read-only. However, the memory array is not protected by this mode. Hardware Write Protection requires the setting of WP = 0 and WPEN = 1. Otherwise, it is disabled. WPEN cannot be altered from 1 to 0 if WP is already set to Low. (Table 4 for write protection) Level Status Register Bits Array Addresses Protected BP1 BP0 0 0 0 None 1 (1/4) 0 1 1800h-1FFFh 2 (1/2) 1 0 1000h-7FFFh 3 (All) 1 1 0000h-7FFFh |
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