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EC24C512CM1GT Datasheet(PDF) 5 Page - E-CMOS Corporation |
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EC24C512CM1GT Datasheet(HTML) 5 Page - E-CMOS Corporation |
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5 / 16 page  EC24C512C 512K bits Two-wire Serial EEPROM E-CMOS Corp. (www.ecmos.com.tw) Page 5 of 16 5C26N-Rev.F001 Write Operation Byte Write In the Byte Write mode, the Master device sends the Start condition and the Slave address information (with the R/W set to Zero) to the Slave device. After the Slave generates an ACK, the Master sends the byte address that is to be written into the address pointer of the EC24C512C. After receiving another ACK from the Slave, the Master device transmits the data byte to be written into the address memory location. The EC24C512C acknowledges once more and the Master generates the Stop condition, at which time the device begins its internal programming cycle. While this internal cycle is in progress, the device will not respond to any request from the Master device. Page Write The EC24C512C is capable of 128-byte Page-Write operation. A Page-Write is initiated in the same manner as a Byte Write, but instead of terminating the internal Write cycle after the first data word is transferred, the Master device can transmit up to 127 more bytes. After the receipt of each data word, the EEPROM responds immediately with an ACK on SDA line, and the seven lower order data word address bits are internally incremented by one, while the higher order bits of the data word address remain constant. If a byte address is incremented from the last byte of a page, it returns to the first byte of that page. If the Master device should transmit more than 128 bytes prior to issuing the Stop condition, the address counter will “roll over,” and the previously written data will be overwritten. Once all 128 bytes are received and the Stop condition has been sent by the Master, the internal programming cycle begins. At this point, all received data is written to the EC24C512C in a single Write cycle. All inputs are disabled until completion of the internal Write cycle. Acknowledge (ACK) Polling The disabling of the inputs can be used to take advantage of the typical Write cycle time. Once the Stop condition is issued to indicate the end of the host's Write operation, the EC24C512C initiates the internal Write cycle. ACK polling can be initiated immediately. This involves issuing the Start condition followed by the Slave address for a Write operation. If the EEPROM is still busy with the Write operation, no ACK will be returned. If the EC24C512C has completed the Write operation, an ACK will be returned and the host can then proceed with the next Read or Write operation. Write Identification Page The Identification Page(128 bytes) is an additional page which can be written and (later) permanently locked in Read-only mode. It is written by issuing the Write Identification Page instruction. This instruction uses the same protocol and format as Page Write (into memory array), except for the following differences: ● Device type identifier=1011b ● MSB address bits A15/A7 are don’t care except for address bit A10 which must be ‘0’. LSB address bits A6/A0 define the byte address inside the Identification page. If the Identification page is locked, the data bytes transferred during the Write Identification Page instruction are not acknowledged (NoACK). Lock Identification Page The Lock Identification Page instruction (Lock ID) permanently locks the Identification page In Read-only mode. The lock ID instruction is similar to Byte Write (into memory array) with the following specific condition: ● Device type identifier=1011b ● Address bit A10 must be ‘1’; all other address bits are don’t care ● The data byte must be equal to the binary value xxxx xx1x, where x is don’t care |
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