EC24C512A

512K bitsTwo-wire Serial EEPROM

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4B12N-Rev.P001

Marking Information

Package type

Part Number

Marking

Marking Information

SOP-8

EC24C512AM1GX

24C512A

LLLLL

YYWWT

512 is the memory of production.

LLLLL is the last five numbers of wafer lot number

YYWW is Date Code.

T is tracking Code ,T=X

TSSOP-8

EC24C512AE1GX

PDIP-8

EC24C512AP1GX

Memory Organization

EC24C512A, 512K SERIAL EEPROM: Internally organized with 512 pages of 128 bytes each, the 512K

requires an 16-bit data word address for random word addressing.

Device Operation

CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the

SDA pin may change only during SCL low time periods (see to Figure1). Data changes during SCL high

periods will indicate a start or stop condition as defined below.

START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede

any other command (see to Figure 2).

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence,

the stop command will place the EEPROM in a standby power mode (see to Figure 2).

ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit

words. The EEPROM sends a "0" to acknowledge that it has received each word. This happens during the

ninth clock cycle

STANDBY MODE: The EC24C512A features a low-power standby mode which is enabled:

(a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations

MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be reset

by following these steps:

1. Clock up to 9 cycles.

2. Look for SDA high in each cycle while SCL is high.

3. Create a start condition.