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BQ7790501PWR Datasheet(PDF) 9 Page - Texas Instruments |
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BQ7790501PWR Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 47 page  9 bq77904, bq77905 www.ti.com SLUSCM3G – JUNE 2016 – REVISED SEPTEMBER 2017 Product Folder Links: bq77904 bq77905 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated Electrical Characteristics (continued) Typical values stated at TA = 25ºC and VDD = 16 V (bq77904) or 20 V (bq77905). MIN and MAX values stated with TA = –40ºC to +85ºC and VDD = 3 to 20 V (bq77904) or VDD = 3 to 25 V (bq77905) unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (2) Not production tested parameters. Specified by design (3) Device is in no fault state prior to entering Customer Test Mode. VCTR2 Enable FET driver (Stacked) Enabled > MIN VDD + 2.2 V VCTR(DIS) Disable FET driver Disabled between MIN and MAX 2.04 VDD + 0.7 V VCTR(MAXV) CTRC and CTRD clamp voltage ICTR = 600nA VDD + 2.8 VDD + 4 VDD + 5 V tCTRDEG_ON) (2) CTRC and CTRD de-glitch for ON signal 7 ms tCTRDEG_OFF (2) CTRC and CTRD de-glitch for OFF signal 7 ms CURRENT STATE COMPARATOR V(STATE_D1) Discharge qualification threshold1 Measured at SRP-SRN -3 –2 -1 mV V(STATE_C1) Charge qualification threshold1 Measured at SRP-SRN 1 2 3 mV tSTATE (2) State detection qualification time 1.2 ms LOAD REMOVAL DETECTION VLD(CLAMP) LD clamp voltage I(LDCLAMP) = 300 µA 16 18 20.5 V ILD(CLAMP) LD clamp current V(LDCLAMP) = 18 V 450 µA VLDT LD threshold Load removed < when VLDT 1.25 1.3 1.35 V RLD(INT) LD input resistance when enabled Measured to VSS 160 250 375 kΩ tLD_DEG LD detection de-glitch 1 1.5 2.3 ms CCFG PIN V(CCFGL) CCFG threshold low (ratio of VAVDD) 3 cell configuration 10 %AVDD V(CCFGH) CCFG threshold high (ratio of VAVDD) 4 cell configuration 65 100 %AVDD V(CCFGHZ) CFG threshold high-Z (ratio of VAVDD) 5 cell configuration, CCFG floating, internally biased 25 33 45 %AVDD tCCFG_DEG (2) CCFG de-glitch 6 ms CUSTOMER TEST MODE V(CTM) Customer test mode entry voltage at VDD VDD > VC5 + V(CTM), TA = 25°C 8.5 10 V tCTM_ENTRY (3) Delay time to enter and exit customer test mode VDD > VC5 + V(CTM), TA = 25°C 50 ms tCTM_DELAY (3) Delay time of faults while in customer test mode TA = 25°C 200 ms tCTM_OC_REC (3) Fault recovery time of OCD1, OCD2, and SCD faults while in customer test mode 1 s and 8 s options, TA = 25°C 100 ms |
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