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ADC32RF82 Datasheet(PDF) 6 Page - Texas Instruments |
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ADC32RF82 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 151 page  6 ADC32RF82 SBAS869 – SEPTEMBER 2017 www.ti.com Product Folder Links: ADC32RF82 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated (1) See the Power Consumption in Different Modes section for more details. (2) Full-scale signal is applied to the analog inputs of all active channels. (3) When used in dc-coupling mode, the common-mode voltage at the analog inputs should be kept within VCM ±25 mV for best performance. (4) Crosstalk is measured with a –2-dBFS input signal on aggressor channel and no input on the victim channel. (5) See Figure 64. 6.5 Electrical Characteristics typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C; and chip sampling rate = 2457.6 MSPS, 50% clock duty cycle, DDC-bypassed performance, AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER CONSUMPTION(1) (Dual-Channel Operation, Both Channels A and B are Active; Divide-by-4, Complex Output Mode(2)) IAVDD19 1.9-V analog supply current fS = 2457.6 MSPS 1729 1950 mA IAVDD 1.15-V analog supply current fS = 2457.6 MSPS 850 1153 mA IDVDD 1.15-V digital supply current fS = 2457.6 MSPS 1500 1760 mA PD Power dissipation fS = 2457.6 MSPS 5.99 6.86 W Global power-down power dissipation 360 mW ANALOG INPUTS Resolution 14 Bits Differential input full-scale 1.35 VPP VIC Input common-mode voltage 1.2(3) V RIN Input resistance Differential resistance at dc 65 Ω CIN Input capacitance Differential capacitance at dc 2 pF VCM common-mode voltage output 1.2 V Analog input bandwidth (–3-dB point) ADC driven with 50-Ω source 3200 MHz ISOLATION Crosstalk isolation between channel A and channel B(4) fIN = 100 MHz 100 dBc fIN = 900 MHz 99 fIN = 1800 MHz 95 fIN = 2700 MHz 86 fIN = 3500 MHz 85 CLOCK INPUT(5) Input clock frequency 1.5 2.5 GSPS Differential (peak-to-peak) input clock amplitude 0.5 1.5 2.5 VPP Input clock duty cycle 45% 50% 55% Internal clock biasing 1.0 V Internal clock termination (differential) 100 Ω |
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