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AD9953ASV Datasheet(PDF) 8 Page - Analog Devices |
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AD9953ASV Datasheet(HTML) 8 Page - Analog Devices |
8 / 42 page PRELIMINARY TECHNICAL DATA AD9953 Hardware Pin Descriptions Pin # Pin Name I/O Description 1 I/O UPDATE I The rising edge transfers the contents of the internal buffer memory to the IO Registers. 2,34 DVDD I Digital power supply pins. 3,33, 42 DGND I Digital power ground pins. 4,6, 13,16, 18,19, 25,27, 29 AVDD I Analog power supply pins. 5,7, 14,15, 17,22, 26, 30,31 32 AGND I Analog power ground pins. 8 OSCB/REFCLKB I Complementary reference clock/oscillator input (400MHz max.). NOTE: When the REFCLK port is operated in single-ended mode, then REFCLKB should be decoupled to AVDD with a 0.1 µF capacitor. 9 OSC/REFCLK I Reference clock/oscillator input (400 MHz max.). See Clock Input section of datasheet for details on the REFCLK/OSCILLATOR operation. 10 Crystal Out O Output of the oscillator section. 11 ClkModeSelect I Control pin for the oscillator section. When high, the oscillator section is enabled. When low, the oscillator section is bypassed. 12 LOOP_FILTER I This Pin provides the connection for the external zero compensation network of the REFCLK Multiplier’s PLL loop filter. The network consists of a 1K ohm resistor in series with a 0.1 µF capacitor tied to AVDD. 20 IOUTB O Complementary DAC output. 21 IOUT O DAC output. 23 DACBP I DAC “biasline” decoupling pin. 24 DAC_Rset I A resistor (3.85K Ω nominal) connected from AGND to DAC_Rset establishes the reference current for the DAC. 28 NC O No connect. 35 PwrDwnCtl I Input pin used as an external power down control. See the External Power Down Control section of this document for details. REV. PrB 1/30/03 Page 8 Analog Devices, Inc. |
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