A80960JD-40 datasheet(1/59 Pages) INTEL

Part #	A80960JD-40

Description	3.3 V EMBEDDED 32-BIT MICROPROCESSOR

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Manufacturer	INTEL [Intel Corporation]

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November 1996

Order Number: 272971-001

PRODUCT PREVIEW

80960JD

3.3 V EMBEDDED 32-BIT MICROPROCESSOR

• 3.3 V, 5 V Tolerant, Version of the 80960JD Processor

Figure 1.

80960JD Microprocessor

s Pin/Code Compatible with all 80960Jx

Processors

s High-Performance Embedded Architecture

— One Instruction/Clock Execution

— Core Clock Rate is 2x the Bus Clock

— Load/Store Programming Model

— Sixteen 32-Bit Global Registers

— Sixteen 32-Bit Local Registers (8 sets)

— Nine Addressing Modes

— User/Supervisor Protection Model

s Two-Way Set Associative Instruction Cache

— 80960JD - 4 Kbyte

— Programmable Cache Locking

Mechanism

s Direct Mapped Data Cache

— 80960JD - 2 Kbyte

— Write Through Operation

s On-Chip Stack Frame Cache

— Seven Register Sets Can Be Saved

— Automatic Allocation on Call/Return

— 0-7 Frames Reserved for High-Priority

Interrupts

s On-Chip Data RAM

— 1 Kbyte Critical Variable Storage

— Single-Cycle Access

s 3.3 V Supply Voltage

— 5 V Tolerant Inputs

— TTL Compatible Outputs

s High Bandwidth Burst Bus

— 32-Bit Multiplexed Address/Data

— Programmable Memory Configuration

— Selectable 8-, 16-, 32-Bit Bus Widths

— Supports Unaligned Accesses

— Big or Little Endian Byte Ordering

s High-Speed Interrupt Controller

— 31 Programmable Priorities

— Eight Maskable Pins plus NMI

— Up to 240 Vectors in Expanded Mode

s Two On-Chip Timers

— Independent 32-Bit Counting

— Clock Prescaling by 1, 2, 4 or 8

— lnternal Interrupt Sources

s Halt Mode for Low Power

s IEEE 1149.1 (JTAG) Boundary Scan

Compatibility

s Packages

— 132-Lead Pin Grid Array (PGA)

— 132-Lead Plastic Quad Flat Pack (PQFP)

PIN 1

132

99

66

33

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A80960JD

NG80960JD

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