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74LVT125DB Datasheet(PDF) 8 Page - NXP Semiconductors |
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74LVT125DB Datasheet(HTML) 8 Page - NXP Semiconductors |
8 / 15 page 9397 750 14703 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 05 — 10 February 2005 8 of 15 Philips Semiconductors 74LVT125 3.3 V quad buffer; 3-state VM = 1.5 V. a. Input pulse definition Test data is given in Table 9. Definitions test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times. b. Test circuit Fig 8. Load circuitry for switching times Table 9: Test data Input Load VEXT VI fi tW tr, tf CL RL tPHZ, tPZH tPLZ, tPZL tPLH, tPHL 2.7 V ≤ 10 MHz 500 ns ≤ 2.5 ns 50 pF 500 Ω GND 6 V open 001aac221 VM VM tW tW 10 % 90 % 90 % 0 V VI VI negative pulse positive pulse 0 V VM VM 90 % 10 % 10 % tTHL(tf) tTLH(tr) tTLH(tr) tTHL(tf) VEXT VCC VI VO mna616 D.U.T. CL RT RL RL PULSE GENERATOR |
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