preliminary

preliminary

BATTERY-BUFFERED HALL MULTITURN ENCODER

Rev B3, Page 9/33

OPERATING REQUIREMENTS: Serial and Parallel Interface

Operating conditions:

VDD = 3.0...5.5 V, VBAT < VDD + 1.0 V, Tj = -40...125 °C, fslow calibrated to 34 kHz with IBIAS, unless otherwise stated.

Item

Symbol

Parameter

Conditions

Unit

No.

Min.

Max.

Serial Interface Mode (SSI or Chain Mode if Applicable)

SSI Request after VDD Power-on

10

µs

Request Signal lo Level Duration

50

ns

Permissible Clock Period

due to Elec. Char. B02

0.25

µs

Permissible Clock Frequency

due to Elec. Char. B02

10

MHz

Clock Signal hi Level Duration

50

ns

Clock Signal lo Level Duration

50

ns

Cyclic Multiturn Data Frame Request

Interval

85

µs

Setup Time:

Data stable before clock edge hi → lo

refer to Fig. 2

30

ns

Hold Time:

Data stable after clock edge hi → lo

refer to Fig. 2

30

ns

10

µs

Permissible Input Clock Frequency

B02

100

kHz

Parallel Encoder Mode (SEL = High)

Length of Start Pulse on PRE Pin

see Figure 11 on Page 21

1

µs

Time Between Two Consecutive Sensor

Read Cycles

see Figure 11 on Page 21

30

µs

CLK

DO

REQ

t

req

MT MSB

t

L1

t

L2

t

p

t

c

t

out

Sync 2

Sync 0

NERR

NWRN

t

frame

Sync 1

Absolute Data Multiturn

(Synchronization)

(Error + Warning)

Timeout

PARITY

(Parity)

...

MT LSB

...

PCR 7

(Period Count per Revolution)

PCR 0

Figure 1: I/O line signals of the serial interface in SSI mode (INT_MODE = 0)

CLK

DO

MT MSB

MSB-1

MSB-2

...

MT LSB

t

c

ST MSB

DIN

t

frame

DIN

DI

ST MSB

MSB-1

...

ST LSB

ST LSB

t

p

DIN

DIN

t

out

NSL

to iC-LNB/LNG only

Sample ST MSB

for synchronisation

(first CLK rising edge)

t

S

t

H

…

Figure 2: I/O line signals of the serial interface in chain mode (INT_MODE = 1).