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IC-MU Datasheet(PDF) 9 Page - IC-Haus GmbH |
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IC-MU Datasheet(HTML) 9 Page - IC-Haus GmbH |
9 / 66 page iC-MU MAGNETIC OFF-AXIS POSITION ENCODER - POLE WIDTH 1.28MM Rev D1, Page 9/66 ELECTRICAL CHARACTERISTICS Operating conditions: VPD = VPA = 5 V ±10%, Tj = -40. . . 125°C, IBP calibrated to 200 µA, reference is VNA = VND, unless otherwise stated Item Symbol Parameter Conditions Unit No. Min. Typ. Max. 503 GX Adjustable Gain(SIN)/Gain(COS) GX_x = 0x00 0 % GX_x = 0x3F 9 10 % GX_x = 0x7F -9 -8.5 % 504 VOS Adjustable Offset Calibration VOS_x = 0x3F 60 70 mV VOS_x = 0x7F -70 -60 mV 505 PHM Adjustable Phase Calibration Master Track PH_M = 0x3F 6 7 ° PH_M = 0x7F -7 -6 ° 506 PHN Adjustable Phase Calibration Nonius Track PH_N = 0x3F 11.25 13 ° PH_N = 0x7F -13 -11.25 ° 507 Vampl Signal Level Controller chip internally, Vampl = Vpp(PSINx)+Vpp(NSINx), ENAC = 1 3.2 4 4.8 Vpp 508 Vae()lo Signal Monitoring Threshold lo Vae()lo = Vpp(PSINx)+Vpp(NSINx) 1.2 2.8 Vpp 509 Vae()hi Signal Monitoring Threshold hi Vae()hi = Vpp(PSINx)+VPP(NSINx) 5 6.3 Vpp Sine-To-Digital Conversion 601 Aabs Absolute Angular Accuracy ideal input signals, reference to 12 Bit of sine period 2 LSB 602 Arel Relative Angular Accuracy FILT = 0x2 2 LSB FILT = 0x7 1/4 LSB ideal input signals, reference to 12 Bit of sine period, f = 1 KHz Nonius Calculation 701 Pnon Permissible Track deviation Master vs. Nonius 16 periods, MPC = 0x4 10 DEG 32 periods, MPC = 0x5 5 DEG 64 periods, MPC = 0x6 2.5 DEG referenced to 360° of Master sine period Digital Output Port PA1..3, MTC, SCL, SDA 801 Vs()hi Saturation Voltage hi Pins PA1..3, MTC Vs()hi = V(VPD) - V(), I() = -4 mA 0.4 V 802 Vs()lo Saturation Voltage lo I() = 4 mA versus VND 0.4 V 803 Isc()hi Short-Circuit Current hi Pins PA1..3, MTC V() = V(VND), 25 °C -90 -50 mA 804 Isc()lo Short-Circuit Current lo V() = V(VPD), 25 °C 50 90 mA 805 tr() Rise Time CL = 50 pF 60 ns 806 tf() Fall Time CL = 50 pF 60 ns 807 Ilk(PA3) Leakage Current at PA3 MODEA=0, PA0 = hi -5 5 µA 808 f(SCL) Frequency at SCL normal mode 80 kHz during start-up 70 kHz Digital Input Port PA0..2, MTD, SCL, SDA 901 Vt()hi Threshold Voltage hi 2 V 902 Vt()lo Threshold Voltage lo 0.8 V 903 Vt()hys Hysteresis Vt()hys = Vt()hi - Vt()lo 150 mV 904 Ipu() Pull-Up Current Pins PA0..2, MTD V() = 0 V . . . V(VPD)-1 V -60 -30 -6 µA 905 Ipu() Pull-Up Current Pins SCL, SDA V() = 0 V . . . V(VPD)-1 V -800 -300 -80 µA 906 f() Permissible Input Frequency 10 MHz Analog/Digital Output Port PB0..3 A01 I()buf Analog Driver Current -1 1 mA A02 fg()ana Analog Bandwidth 100 kHz A03 Isc()hi,ana Analog Short-Circuit Current hi V() = V(VND) -1.5 mA A04 Isc()lo,ana Analog Short-Circuit Current lo V() = V(VPD) 1.5 mA A05 Rout(),ana Output Resistor, Analog Mode I() = 1 mA 500 Ω A06 Vs()hi,dig Digital Saturation Voltage hi Vs() = V(VPD) - V(), I() = -4 mA 0.5 V A07 Vs()lo,dig Digital Saturation Voltage lo I() = 4 mA 0.5 V A08 Isc()hi,dig Short-Circuit Current hi V() = V(VPD) -60 -35 mA |
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