GS8672D19/37BE-450/400/375/333/300

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 1.02c 8/2017

7/28

© 2011, GSI Technology

Special Functions

Byte Write Control

Byte Write Enable pins are sampled at the same time that Data In is sampled. A High on the Byte Write Enable pin associated with

a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be

stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven High or Low

during the data in sample times in a write sequence.

Each write enable command and write address loaded into the RAM provides the base address for a 4-beat data transfer. The x18

version of the RAM, for example, may write 72 bits in association with each address loaded. Any 9-bit byte may be masked in any

write sequence.

Note: If “Half Write” operations (i.e., write operations in which a BWn pin is asserted for only half of a DDR write data transfer

on the associated 9-bit data bus, causing only 9 bits of the 18-bit DDR data word to be written) are initiated, the on-chip ECC will

be disabled for as long as the SRAM remains powered up thereafter. This must be done because ECC is implemented across entire

18-bit data words, rather than across individual 9-bit data bytes.

Byte Write Truth Table

The truth table below applies to write operations to Address "m", where Address "m" is the 18-bit memory location comprising the

2 beats of DDR write data associated with each BWn pin in a given clock cycle.

BWn

Input Data Byte n

Operation

Result



K

(Beat 1)



K

(Beat 2)



K

(Beat 1)



K

(Beat 2)

0

0

D0

D1

Full Write

D0 and D1 written to Address m

0

1

D0

X

Half Write

Only D0 written to Address m

1

0

X

D1

Half Write

Only D1 written to Address m

1

1

X

X

Abort

Address m unchanged

Notes:

1. BW0 is associated with Input Data Byte D[8:0].

2. BW1 is associated with Input Data Byte D[17:9].

3. BW2 is associated with Input Data Byte D[26:18] (in x36 only).

4. BW3 is associated with Input Data Byte D[35:27] (in x36 only).

5. ECC is disabled if a “Half Write” operation is initiated.

6. Although these devices execute Burst of 4 (i.e., 4-beat) write operations, for the purposes of this table they should be viewed as a pair of

Burst of 2 (i.e., 2-beat) write operations. As such, valid/allowable Burst of 4 write operations only comprise (any combination of) Burst of 2

Full Write and/or Abort Write operations, as defined above.