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X9530 Datasheet(PDF) 4 Page - Xicor Inc. |
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X9530 Datasheet(HTML) 4 Page - Xicor Inc. |
4 / 30 page X9530 Characteristics subject to change without notice. 4 of 30 REV 3.7 8/26/04 www.xicor.com PRINCIPLES OF OPERATION CONTROL AND STATUS REGISTERS The Control and Status Registers provide the user with a mechanism for changing and reading the value of various parameters of the X9530. The X9530 contains seven Control, one Status, and several Reserved registers, each being one Byte wide (See Figure 1). The Control registers 0 through 6 are located at memory addresses 80h through 86h respectively. The Status register is at memory address 87h, and the Reserved registers at memory address 88h through 8Fh. All bits in Control register 6 always power up to the logic state “0”. All bits in Control registers 0 through 5 power up to the logic state value kept in their corresponding nonvolatile memory cells. The nonvolatile bits of a register retain their stored values even when the X9530 is powered down, then powered back up. The nonvolatile bits in Control 0 through Control 5 registers are all preprogrammed to the logic state “0” at the factory. Bits indicated as “Reserved” are ignored when read, and must be written as “0”, if any Write operation is performed to their registers. A detailed description of the function of each of the Control and Status register bits follows: Control Register 0 This register is accessed by performing a Read or Write operation to address 80h of memory. BL1, BL0: BLOCK LOCK PROTECTION BITS (NON-VOLATILE) These two bits are used to inhibit any write operation to certain addresses within the memory array. The protected region of memory is determined by the values of the two bits as shown in the table below: If the user attempts to perform a write operation to a protected region of memory, the operation is aborted without changing any data in the array. Notice that if the Write Protect (WP) input pin of the X9530 is active (LOW), then any write operation to the memory is inhibited, irrespective of the Block Lock bit settings. VRM: VOLTAGE REFERENCE PIN MODE (NON-VOLATILE) The VRM bit configures the Voltage Reference pin (VRef) as either an input or an output. When the VRM bit is set to “0” (default), the voltage at pin VRef is an output from the X9530’s internal voltage reference. When the VRM bit is set to “1”, the voltage reference for the VRef pin is external. See Figure 2. ADCIN: A/D CONVERTER INPUT SELECT (NON-VOLATILE) The ADCIN bit selects the input of the on-chip A/D converter. When the ADCIN bit is set to “0” (default), the output of the on-chip temperature sensor is the input to the A/D converter. When the ADCIN bit is set to “1”, the input to the A/D converter is the voltage at the VSense pin. See Figure 4. ADCFILTOFF: ADC FILTERING CONTROL (NON-VOLATILE) When this bit is“1”, the status register at 87h is updated after every conversion of the ADC. When this bit is “0” (default), the status register is updated after four consecutive conversions with the same result. NV1234: CONTROL REGISTERS 1, 2, 3, AND 4 VOLATILITY MODE SELECTION BIT (NON-VOLATILE) When the NV1234 bit is set to “0” (default), bytes written to Control registers 1, 2, 3, and 4 are stored in volatile cells, and their content is lost when the X9530 is powered down. When the NV1234 bit is set to “1”, bytes written to Control registers 1, 2, 3, and 4 are stored in both volatile and nonvolatile cells, and their value doesn’t change when the X9530 is powered down and powered back up. See “Writing to Control Registers” on page 17. I1DS: CURRENT GENERATOR 1 DIRECTION SELECT BIT (NON-VOLATILE) The I1DS bit sets the polarity of Current Generator 1, DAC1. When this bit is set to “0” (default), the Current Generator 1 of the X9530 is configured as a Current Source. Current Generator 1 is configured as a Current Sink when the I1DS bit is set to “1”. See Figure 5. Protected Addresses (Size) Partition of array locked 0 0 None (Default) None (Default) 0 1 00h to 7Fh (128 bytes) GPM 1 0 00h to 7Fh and 90h to CFh (192 bytes) GPM, LUT1 1 1 00h to 7Fh and 90h to 10Fh (256 bytes) GPM, LUT1, LUT2 |
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