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MC68HC811E2CFN2 Datasheet(PDF) 34 Page - Motorola, Inc |
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MC68HC811E2CFN2 Datasheet(HTML) 34 Page - Motorola, Inc |
34 / 268 page Operating Modes and On-Chip Memory Data Sheet M68HC11E Family — Rev. 5 34 Operating Modes and On-Chip Memory MOTOROLA The expansion bus is made up of ports B and C, and control signals AS (address strobe) and R/W (read/write). R/W and AS allow the low-order address and the 8-bit data bus to be multiplexed on the same pins. During the first half of each bus cycle address information is present. During the second half of each bus cycle the pins become the bidirectional data bus. AS is an active-high latch enable signal for an external address latch. Address information is allowed through the transparent latch while AS is high and is latched when AS drives low. The address, R/W, and AS signals are active and valid for all bus cycles, including accesses to internal memory locations. The E clock is used to enable external devices to drive data onto the internal data bus during the second half of a read bus cycle (E clock high). R/W controls the direction of data transfers. R/W drives low when data is being written to the internal data bus. R/W will remain low during consecutive data bus write cycles, such as when a double-byte store occurs. Refer to Figure 2-1. NOTE: The write enable signal for an external memory is the NAND of the E clock and the inverted R/W signal. Figure 2-1. Address/Data Demultiplexing 2.2.3 Test Mode Test mode, a variation of the expanded mode, is primarily used during Motorola’s internal production testing; however, it is accessible for programming the HC373 MCU ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 ADDR15 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 ADDR7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 DATA7 D2 D3 D4 D5 D6 D7 D8 D1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q1 OE LE PC6 PC5 PC4 PC3 PC2 PC1 PC0 PC7 AS PB6 PB5 PB4 PB3 PB2 PB1 PB0 PB7 R/W E WE OE Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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