- 11 -

Rev 2.0

Nov. 2003

K7N401801B

K7N403601B

Notes : 1. The above parameters are also guaranteed at industrial temperature range.

2. All address inputs must meet the specified setup and hold times for all rising clock(CLK) edges when ADV is sampled low and CS is sampled

low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.

3. Chip selects must be valid at each rising edge of CLK(when ADV is Low) to remain enabled.

4. A write cycle is defined by WE low having been registered into the device at ADV Low, A Read cycle is defined by WE High with ADV Low,

Both cases must meet setup and hold times.

(0

It is not possible for two SRAMs on the same board to be at such different voltage and temperature.

PARAMETER

Symbol

-13

UNIT

Min

Max

Cycle Time

tCYC

7.5

-

ns

Clock Access Time

tCD

-

4.2

ns

Output Enable to Data Valid

tOE

-

4.2

ns

Clock High to Output Low-Z

tLZC

1.5

-

ns

Output Hold from Clock High

tOH

1.5

-

ns

Output Enable Low to Output Low-Z

tLZOE

0

-

ns

Output Enable High to Output High-Z

tHZOE

-

3.8

ns

Clock High to Output High-Z

tHZC

-

3.8

ns

Clock High Pulse Width

tCH

3.0

-

ns

Clock Low Pulse Width

tCL

3.0

-

ns

Address Setup to Clock High

tAS

1.5

-ns

CKE Setup to Clock High

tCES

1.5

-ns

Data Setup to Clock High

tDS

1.5

-ns

Write Setup to Clock High (WE, BWX)

tWS

1.5

-ns

Address Advance Setup to Clock High

tADVS

1.5

-ns

Chip Select Setup to Clock High

tCSS

1.5

-ns

Address Hold from Clock High

tAH

0.5

-

ns

CKE Hold from Clock High

tCEH

0.5

-

ns

Data Hold from Clock High

tDH

0.5

-

ns

Write Hold from Clock High (WE, BWEX)

tWH

0.5

-

ns

Address Advance Hold from Clock High

tADVH

0.5

-

ns

Chip Select Hold from Clock High

tCSH

0.5

-

ns

ZZ High to Power Down

tPDS

2

-

cycle

ZZ Low to Power Up

tPUS

2

-

cycle

Output Load(B),

Dout

353

Ω / 1538Ω

5pF*

+3.3V for 3.3V I/O

319

Ω / 1667Ω

Fig. 1

* Including Scope and Jig Capacitance

Output Load(A)

Dout

Zo=50

Ω

RL=50

Ω

VL=1.5V for 3.3V I/O

/+2.5V for 2.5V I/O

30pF*