Electronic Components Datasheet Search |
|
MB4L16MMNR2G Datasheet(PDF) 1 Page - ON Semiconductor |
|
MB4L16MMNR2G Datasheet(HTML) 1 Page - ON Semiconductor |
1 / 12 page © Semiconductor Components Industries, LLC, 2016 August, 2016 − Rev. 4 1 Publication Order Number: NB4L16M/D NB4L16M 2.5 V/3.3 V, 5 Gb/s Multi Level Clock/Data Input to CML Driver/Receiver/Buffer/ Translator with Internal Termination Description The NB4L16M is a differential driver/receiver/buffer/translator which can accept LVPECL, LVDS, CML, HSTL, LVCMOS/LVTTL and produce 400 mV CML output. The device is capable of receiving, buffering, and translating a clock or data signal that is as small as 75 mV operating up to 3.5 GHz or 5.0 Gb/s, respectively. As such, it is ideal for SONET, GigE, Fiber Channel and backplane applications (see Table 6 and Figures 20, 21 22, and 23). Differential inputs incorporate internal 50 W termination resistors and accept LVPECL (Positive ECL), LVTTL/LVCMOS, CML, HSTL or LVDS. The differential 16 mA CML output provides matching internal 50 W termination, and 400 mV output swing when externally receiver terminated, 50 W to VCC (see Figure 19). These features provide transmission line termination on chip, at the receiver and driver end, eliminating any use of additional external components. The VBB, an internally generated voltage supply, is available to this device only. For single-ended input configuration, the unused complementary differential input is connected to VBB as a switching reference voltage. The VBB reference output can be used also to re-bias capacitor coupled differential or single-ended output signals. For the capacitor coupled input signals, VBB should be connected to the VTD pin and bypassed to ground with a 0.01 mF capacitor. When not used VBB should be left open. This device is housed in a 3x3 mm 16 pin QFN package. Application notes, models, and support documentation are available at www.onsemi.com. Features • Maximum Input Clock Frequency up to 3.5 GHz • Maximum Input Data Rate up to 5.0 Gb/s • < 0.7 ps Maximum Clock RMS Jitter • < 10 ps Maximum Data Dependent Jitter at 2.5 Gb/s • 220 ps Typical Propagation Delay • 60 ps Typical Rise and Fall Times • CML Output with Operating Range: ♦ VCC = 2.375 V to 3.6 V with VEE = 0 V • CML Output Level (400 mV Peak-to-Peak Output), Differential Output Only • 50 W Internal Input and Output Termination Resistors • Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP, EP, and SG Devices • These Devices are Pb-Free, Halogen Free and are RoHS Compliant A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package MARKING DIAGRAM* QFN−16 MN SUFFIX CASE 485G−01 www.onsemi.com 16 NB4L 16M ALYWG G 1 (Note: Microdot may be in either location) 1 ORDERING INFORMATION Device Package Shipping† MB4L16MMNG QFN−16 (Pb-Free) 123 Units/Tube MB4L16MMNR2G QFN−16 (Pb-Free) 3000/Tape & Reel †For information on tape and reel specifications, in- cluding part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *For additional marking information, refer to Application Note AND8002/D. |
Similar Part No. - MB4L16MMNR2G |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |