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74LVC2G86 Datasheet(PDF) 2 Page - NXP Semiconductors

Part # 74LVC2G86
Description  Dual 2-input exclusive-OR gate
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74LVC2G86 Datasheet(HTML) 2 Page - NXP Semiconductors

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9397 750 14506
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 7 February 2005
2 of 15
Philips Semiconductors
74LVC2G86
Dual 2-input exclusive-OR gate
3.
Quick reference data
[1]
CPD is used to determine the dynamic power dissipation (PD in µW).
PD =CPD × VCC2 × fi × N+ ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = number of switching inputs;
∑(C
L × VCC
2
× f
o) = sum of outputs.
[2]
The condition is VI = GND to VCC.
4.
Ordering information
5.
Marking
Table 1:
Quick reference data
GND = 0 V; Tamb =25 °C.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
tPHL,
tPLH
propagation delay inputs
nA, nB to outputs nY
VCC = 1.8 V;
CL = 30 pF; RL =1kΩ
-
3.8
-
ns
VCC = 2.5 V;
CL = 30 pF; RL = 500 Ω
-
2.5
-
ns
VCC = 2.7 V;
CL = 50 pF; RL = 500 Ω
-
3.0
-
ns
VCC = 3.3 V;
CL = 50 pF; RL = 500 Ω
-
2.3
-
ns
VCC = 5.0 V;
CL = 50 pF; RL = 500 Ω
-
1.9
-
ns
CI
input capacitance
-
2.5
-
pF
CPD
power dissipation
capacitance per gate
VCC = 3.3 V
[1] [2] -
15.8
-
pF
Table 2:
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74LVC2G86DP
−40 °C to +125 °C
TSSOP8
plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
SOT505-2
74LVC2G86DC
−40 °C to +125 °C
VSSOP8
plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
SOT765-1
74LVC2G86GT
−40 °C to +125 °C
XSON8
plastic extremely thin small outline package; no leads;
8 terminals; body 1
× 1.95 × 0.5 mm
SOT833-1
Table 3:
Marking
Type number
Marking code
74LVC2G86DP
V86
74LVC2G86DC
V86
74LVC2G86GT
V86


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