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X46402V8-2.9 Datasheet(PDF) 2 Page - Xicor Inc. |
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X46402V8-2.9 Datasheet(HTML) 2 Page - Xicor Inc. |
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2 / 23 page  X46402 Preliminary Information 2 PACKAGE/PINOUTS PIN NAMES PIN DESCRIPTIONS Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with other open drain or open collector out- puts. An open drain requires the use of a pull-up resistor. Write Protect (WP) The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting of the Watchdog Timer control and the memory write protect bits. Reset Output (RESET) RESET is an active LOW, open drain output which goes active whenever Vcc falls below the minimum Vtrip sense level. It will remain active until Vcc rises above the mini- mum Vtrip sense level for 150ms. RESET goes active if the Watchdog Timer is enabled and there is no start bit before the end of the selectable Watchdog time-out period. A serial start bit will reset the Watchdog Timer. RESET also goes active on power up at 1V and remains active for 150ms after the power supply stabilizes. V2 Voltage Fail Output (V2FAIL) V2FAIL is an active LOW, open drain output which goes active whenever V2MON falls below the minimum V2trip sense level. It will remain active until V2MON rises above the minimum V2MON sense level. DEVICE OPERATION Power On Reset Application of power to the X46402 activates a Power On Reset Circuit. This circuit goes active at 1V and pulls the RESET pin active. This signal prevents the system micro- processor from starting to operate with insufficient volt- age or prior to stabilization of the oscillator. When Vcc exceeds the device VTRIP value for 200ms (nominal) the circuit releases RESET allowing the processor to begin executing code. Low Voltage Monitoring During operation, the X46402 monitors the VCC and V2MON levels and compares these with internal, preset voltages. When the internal low voltage detect circuitry senses that V2MON is low, the V2FAIL pin goes active. Typically this would be used by the processor as an interrupt to stop the execution of the code or to do housekeeping in prep- aration for an impending power failure. When the internal low voltage detect circuitry senses that Vcc is low, the following happens: —The RESET pin goes active. —The Flag bit in the control register is set to zero. —Communication to the device is interrupted and any command is aborted. If a serial nonvolatile store is in progress when power fails, the circuitry does not stop the nonvolatile store operation, but attempts to com- plete the operation. The RESET and V2FAIL signals remain active until Vcc voltage drops below 1V. RESET remains active until Vcc returns and exceeds VTRIP for 200ms. V2FAIL remains active until immediately after V2MON returns and exceeds it’s minimum voltage. Watchdog Timer The Watchdog Timer circuit monitors the microprocessor activity by monitoring the Start bit. The microprocessor must send a start bit periodically to prevent a RESET sig- nal. The start bit must occur prior to the expiration of the watchdog time-out period. The state of three nonvolatile control bits in the Control Register determines the watch- dog timer period. The microprocessor can change these watchdog bits, or they may be “locked” by tying the WP pin HIGH and setting the WPEN bit HIGH. VSS Ground SDA Serial Data VCC Power SCL Serial Clock WP Write Protect V2MON Voltage monitor input RESET Low Voltage Detect Output V2FAIL V2 Voltage Fail Output WP VCC V2FAIL SCL VSS V2MON SDA RESET 3 2 4 1 6 7 5 8 8L TSSOP |
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