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MAS9138A1SD06 Datasheet(PDF) 6 Page - Micro Analog systems |
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MAS9138A1SD06 Datasheet(HTML) 6 Page - Micro Analog systems |
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6 / 10 page  6 (10) DA9138.005 12 April, 2006 FUNCTIONS Asynchronous to synchronous converter The synchronous start-stop character, TDI (transmitter data input), is read into the Tx buffer. When the character is available the data bits are transferred as TDO (transmitter data output) with the synchronous timing signal TXC (transmitter clock). The bit rate of TDI must be the same as the TDO rate within -2.5%...+1% or -2.5%...+2.3% tolerance depending on XESR (extended signalling rate) signal. The transmitter adds extra stop bits to the synchronous data stream, if TDI is slower than TDO. The over speed is handled by deleting one stop bit in every 8th character at maximum in the synchronous output data TDO. When extended signal rate (XESR = 0) is used 4th stop bit may be deleted. When the transmitter detects a break signal( at least M bits of start polarity, where M is length of character), it sends 2M + 3 bits of start - polarity to TDO. If the break is longer than 2M + 3 bits, then all bits are transferred to TDO. After a break signal, at least 2M bits of stop polarity must be transmitted before sending further data. Synchronous to asynchronous converter The synchronous RDI (receiver data input) is buffered to recognize the stop and start bits. If a missing stop bit is detected, it is added to the RDO (receiver data output). In this case the stop bits are shortened 12.5% (25% if XESR = 0) during each character. When the receiver gets at least 2M + 3 bits of start polarity, it does not add stop bits to RDO. This enables the break signal to go through the buffer. Converting with higher speed timing An alternative method to handle the over speed in asynchronous data is to boost synchronous timing TXC and RXC by 1-2%. In this mode XHST (higher speed timing) = 0. In this case there is no need to delete any stop bits in the transmitter buffer. The break signal goes through unchanged. On the receiver side the synchronous data, RDI, is transferred directly to the asynchronous output RDO with RXC. Timing selection The MAS9138 requires clock signals in order to function properly. The synchronous data transfer always requires the TXC clock. The clock is used internally for: -shifting data out from the TX buffer (to pin TDO) -detection of the bit rate in order to adjust the internal baud rate generator (only if TSL = 1) The asynchronous data transfer (pins TDI, TDO) is accomplished by generating an internal timing signal for the asychronous circuits. This internal timing signal (16T) is 16 times the TXC bit rate in order to sample the asynchronous data stream (TDI) at the proper speed. The internal clock 16T is either generated from a crystal frequency by dividing it by 8, 16, 21 1/3, 25 3/5, 32, 42 2/3,64,128,256 or 512. Or it can also be generated externally and fed to pin TMG (TSL = 0). This is especially useful if the system already generates a clock which is 16 times the bit clock TXC as shown or if the bit rate is higher than 38.4 kHz. The divider is automatically selected by internal logic by measuring the TXC clock speed (TSL = 1). A crystal oscillator or a resonator can also be connected between pins 2 and 3. The crystal frequency should be 128 x TXCmax. 16 x TXC TXC Timing Circuits MAS 9138 EXTERNALLY GENERATED 16T CLOCK Character Length CL1,CL2 CL1 CL2 Conditions 1 0 8 bits 0 0 9 bits 1 1 10 bits 0 1 11 bits |
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