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S89713 Datasheet(PDF) 7 Page - Seiko Instruments Inc |
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S89713 Datasheet(HTML) 7 Page - Seiko Instruments Inc |
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7 / 24 page  MINI ANALOG SERIES LOW INPUT OFFSET VOLTAGE CMOS OPERATIONAL AMPLIFIER Rev.3.4_00 S-89713 Series 7 Test Circuits (Per circuit) 1. Power supply voltage rejection ratio, input offset voltage VOUT RF RS RS RF + − VCMR = VDD / 2 VDD − + VDDN VSSN NULL D.U.T CF CF • Power supply voltage rejection ratio (PSRR) The power supply voltage rejection ratio (PSRR) can be calculated by the following expression, with VOUT measured at each VDD. Test conditions: VDD = 2.65 V: VDD = VDD1, VOUT = VOUT1 VDD = 5.5 V: VDD = VDD2, VOUT = VOUT2 PSRR = 20 log VDD1 − VDD2 VOUT1 − VDD1 2 − VOUT2 − VDD2 2 × RF + RS RS • Input offset voltage (VIO) VIO = VOUT − VDD 2 × RS RF + RS Figure 5 Test Circuit 1 2. Common-mode input signal rejection ratio, common-mode input voltage range VOUT RF RS RS RF + − VIN VDD − + VDDN VSSN D.U.T CF CF NULL VM = VDD / 2 • Common-mode input signal rejection ratio (CMRR) The common-mode input signal rejection ratio (CMRR) can be calculated by the following expression, with VOUT measured at each VIN. Test conditions: VIN = VCMR Max.: VIN = VIN1, VOUT = VOUT1 VIN = VCMR Min.: VIN = VIN2, VOUT = VOUT2 CMRR = 20 log VIN1 − VIN2 (VOUT1 − VIN1) − (VOUT2 − VIN2) × RF + RS RS • Common-mode input voltage range (VCMR) The common-mode input voltage range is the range of VIN in which VOUT satisfies the common-mode input signal rejection ratio specifications. Figure 6 Test Circuit 2 |
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Similar Description - S89713 |
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