S19110JXXH datasheet(8/46 Pages) SII

Part #	S19110JXXH

Description	FOR AUTOMOTIVEOPERATION HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR

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Manufacturer	SII [Seiko Instruments Inc]

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FOR AUTOMOTIVE 105°C OPERATION HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR

S-19110JxxH to S-19110RxxH Series

Rev.1.3_00

8



Electrical Characteristics

1. VDD detection product

Table 7

(Ta =

−40°C to +105°C unless otherwise specified)

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

Test

Circuit

Detection voltage

*1

−VDET

3.6 V

≤ −VDET(S) ≤ 4.15 V

−VDET(S)

× 0.970

−VDET(S)

× 1.030

V

1

4.2 V

≤ −VDET(S) ≤ 4.95 V

−VDET(S)

× 0.975

−VDET(S)

× 1.025

V

1

Release voltage

*2

+VDET

J / K type

5.0%

≤ VHYS ≤ 20.0%

*3

3.6 V

≤ −VDET(S) ≤ 4.15 V

+VDET(S)

× 0.970

+VDET(S)

× 1.030

V

1

4.2 V

≤ −VDET(S) ≤ 4.95 V

+VDET(S)

× 0.975

+VDET(S)

× 1.025

V

1

J / K type

20.0%

< VHYS ≤ 30.0%

*3

3.6 V

≤ −VDET(S) ≤ 4.15 V

+VDET(S)

× 0.965

+VDET(S)

× 1.035

V

1

4.2 V

≤ −VDET(S) ≤ 4.95 V

+VDET(S)

× 0.970

+VDET(S)

× 1.030

V

1

L / M type

VHYS = 0%

*4

3.6 V

≤ −VDET(S) ≤ 4.15 V

−VDET(S)

× 0.970

−VDET(S)

× 1.030

V

−

4.2 V

≤ −VDET(S) ≤ 4.95 V

−VDET(S)

× 0.975

−VDET(S)

× 1.025

V

−

Current consumption

ISS

J / K / L / M type

VDD =

−VDET − 0.1 V

−

0.60

1.60

μA2

J / K type

VDD =

+VDET + 0.1 V

−

0.60

1.60

μA2

Operation voltage

VDD

−

1.8

−

36.0

V

1

Output current

IOUT

Output transistor

Nch

VDS

*5 = 0.05 V

VDD = 2.9 V, Active "L"

0.33

−

mA

3

VDD = 6.9 V, Active "H"

0.50

−

mA

3

Leakage current

ILEAK

Output transistor

Nch

VDD = 30.0 V, VOUT = 30.0 V,

Active "L"

−

2.0

μA3

VDD = 2.9 V, VOUT = 30.0 V,

Active "H"

−

2.0

μA3

Detection delay time

*6

tRESET

CN = 3.3 nF

8.0

10.0

12.0

ms

4

Release delay time

tDELAY

J / K type

*7

CP = 3.3 nF

8.0

10.0

12.0

ms

4

L / M type

*8

CP = 3.3 nF

8.0

10.0

12.0

ms

4

CP pin discharge

ON resistance

RCP

VDD = 6.9 V, VCP = 0.5 V

0.52

−

1.97

k

Ω

−

CN pin discharge

ON resistance

RCN

VDD = 2.9 V, VCN = 0.5 V

1.0

−

4.24

k

Ω

−

*1.

−VDET: Actual detection voltage value, −VDET(S): Set detection voltage value

*2.

+VDET: Actual release voltage value, +VDET(S): Set release voltage value

*3.

Although the hysteresis width can be set in the range of 5.0% to 30.0%, the release voltage accuracy differs when the

setting range exceeds 20.0%.

*4.

The hysteresis width is "unavailable", so release voltage = detection voltage.

*5.

VDS: Drain-to-source voltage of the output transistor

*6.

The time period from when the pulse voltage of

−VDET(S) + 0.5 V → −VDET(S) − 0.5 V is applied to the VDD pin to when

VOUT reaches VDD / 2, after the power supply voltage (VDD) reaches the release voltage once.

*7.

The time period from when the pulse voltage of

+VDET(S) − 0.5 V → +VDET(S) + 0.5 V is applied to the VDD pin to when

VOUT reaches VDD / 2.

*8.

The time period from when the pulse voltage of

−VDET(S) − 0.5 V → −VDET(S) + 0.5 V is applied to the VDD pin to when

VOUT reaches VDD / 2

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