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FT-5000 Datasheet(PDF) 3 Page - List of Unclassifed Manufacturers |
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FT-5000 Datasheet(HTML) 3 Page - List of Unclassifed Manufacturers |
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3 / 9 page  whenever the interrupt condition is met. See the Neuron C Programmer’s Guide for more information about writing interrupt tasks and handling interrupts. JTAG. The FT 5000 Smart Transceiver provides an interface for the Institute of Electrical and Electronics Engineers (IEEE) Standard Test Access Port and Boundary- Scan Architecture (IEEE 1149.1-1990) of the Joint Test Action Group (JTAG) to allow a Series 5000 chip to be included in the boundary-scan chain for device production tests. A Boundary Scan Description Language (BSDL) file for the FT 5000 Smart Transceiver can be downloaded from Echelon’s Web site. I/O Pins and Counters The FT 5000 Smart Transceiver provides 12 bidirectional I/O pins that are 5V-tolerant and can be configured to operate in one or more of 35 predefined standard input/output models. The chip also has two 16-bit timer/counters that reduce the need for external logic and software development. Memory Architecture The FT 5000 Smart Transceiver uses inexpensive external serial EEPROM and flash memories for non-volatile application and data storage, and optionally for future Neuron firmware upgrades. It has 16KB of ROM and 64KB (44KB user-accessible) of RAM on the chip. It has no on-chip non-volatile memory (EEPROM or flash) for application use. Each chip, however, contains its unique Neuron identifier (Neuron ID) in an on-chip, non-volatile, read-only memory. The application code and configuration data are stored in the external non- volatile memory (NVM) and copied into the internal RAM during device reset; the instructions then execute from internal RAM. Writes to NVM are shadowed in the internal RAM and pushed out to external NVM by the Neuron firmware (see Figure 2). The application does not manage NVM directly. External memories supported. The FT 5000 Smart Transceiver supports two serial interfaces for accessing off-chip, non- volatile memories: serial Inter- Integrated Circuit (I2C) and serial peripheral interface (SPI). EEPROM and flash memory devices can use either the I2C interface or the SPI interface. However, at the time of publication, there are no serial flash parts that use the I2C protocol and meet the required specifications for the Series 5000 external memory interface. External serial EEPROMs and flash devices, which are inexpensive and come in very small form factors, are available from multiple vendors. The FT 5000 Smart Transceiver requires at least 2KB of off-chip memory available in an EEPROM device to store the configuration data. The application code can be stored either in the EEPROM (by using a larger- capacity EEPROM device) or in a flash memory device used in addition to the 2KB (minimum) EEPROM. Thus, the external memory for the FT 5000 Smart Transceiver has one of the configurations listed in Table 1: Con- figura- tion EEPROM Comments I2C SPI SPI 1 ☑ A single I2C EEPROM memory device, from 2KB to 64KB in size. 2 ☑ ☑ One I2C EEPROM (at least 2KB in size, up to 64KB in size, but the system uses only the first 2KB of the EEPROM memory). One SPI flash memory device. 3 ☑ A single SPI EEPROM memory device, from 2KB to 64KB in size. 4 ☑ ☑ One SPI EEPROM (at least 2KB in size, up to 64KB in size, but the system uses only the first 2KB of the EEPROM memory). One SPI flash memory device. Table 1: Allowed External Memory Device Configurations As Table 1 shows, the FT 5000 Smart Transceiver supports using a single EEPROM memory device, or a single EEPROM memory device plus a single flash memory device. If the FT 5000 Smart Transceiver detects an external flash memory device, the flash memory represents the entire user non- volatile memory for the device. That is, any additional EEPROM memory beyond the mandatory 2KB is not used. Using the I2C interface. When using the I2C interface for external EEPROM, the FT 5000 Smart Transceiver is always the master I2C device (see Figure 3). The clock speed supported for the I2C serial memory interface is 400kHz (fast I2C mode). The I2C memory device must specify I2C address 0. Both 1-byte and 2-byte address modes are supported, but 3-byte addressing mode is not. SDA 3.3 V _CS1~ MISO SCL I2C Slave (EEPROM) Series 5000 Chip Figure 3: Using the I2C Interface for External NVM EEPROM Memory Memory devices supported. The FT 5000 Smart Transceiver supports any EEPROM device that uses the SPI or I2C protocol, and meets the clock speed and addressing requirements described above. While all EEPROM devices have a uniform write procedure, flash devices from various manufacturers differ slightly in their write procedure. Thus, a small library routine is stored in the external EEPROM device that helps the system write successfully to the external flash device. Echelon has qualified the following SPI flash memory devices for use with the FT 5000 Smart Transceiver: • Atmel® AT25F512B 512-Kilobit 2.7-volt Minimum SPI Serial Flash Memory. • Numonyx™ M25P05-A 512-Kbit, serial flash memory, 50MHz SPI bus interface. • Silicon Storage Technology SST25VF512A 512 Kbit SPI Serial Flash. Additional devices may be qualified in the future. Memory map. An FT 5000 Smart Transceiver has a memory map of 64KB. A Neuron C application program uses this memory map to organize its memory and data access. The memory map is a logical view of device memory, rather than a physical view, because the chip’s processors only directly access RAM. The memory map divides the FT 5000 Smart Transceiver’s physical 64KB RAM into the following types of logical memory, as shown in Figure 6: • Neuron firmware image (stored in on-chip ROM or external NVM). • On-chip RAM or NVM. Memory ranges for each are configurable within the device hardware template. The non-volatile memory represents www.echelon.com ® |
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