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TSC2200IPW Datasheet(PDF) 2 Page - Burr-Brown (TI) |
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TSC2200IPW Datasheet(HTML) 2 Page - Burr-Brown (TI) |
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2 / 40 page  2 www.ti.com TSC2200 SBAS191F ABSOLUTE MAXIMUM RATINGS(1) VDD to GND ........................................................................ –0.3V to +6.0V VBAT Input Voltage to GND ............................................... –0.3V to +6.0V Analog Input Voltage to GND (except VBAT) ........... –0.3V to VDD + 0.3V Digital Input Voltage to GND ................................... –0.3V to VDD + 0.3V Operating Temperature Range ...................................... –40 °C to +105°C Storage Temperature Range ......................................... –65 °C to +150°C Junction Temperature (TJ Max) .................................................... +150°C TSSOP Package Power Dissipation .................................................... (TJ Max – TA)/θJA θ JA Thermal Impedance .......................................................... 90°C/W Lead Temperature, Soldering Vapor Phase (60s) ............................................................ +215 °C Infrared (15s) ..................................................................... +220 °C NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. INTEGRAL SPECIFIED LINEARITY PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT ERROR (LSB) PACKAGE-LEAD DESIGNATOR(1) RANGE MARKING NUMBER MEDIA, QUANTITY TSC2200 ±2 TSSOP-28 PW –40 °C to +85°C TSC2200I TSC2200IPW Rails, 50 "" " " " " TSC2200IPWR Tape and Reel, 2000 TSC2200 ±2 QFN-32 RHB –40 °C to +85°C TSC2200I TSC2200IRHB Tubes, 72 "" " " " " TSC2200IRHBR Tape and Reel, 2500 NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper han- dling and installation procedures can cause damage. ESD damage can range from subtle performance degrada- tion to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. TIMING DIAGRAM All specifications typical at –40 °C to +85°C, +V DD = +2.7V. t td t Lag t dis t Lead t sck t wsck t wsck t hi t su t ho t a t v t r t f SS SCLK MSB OUT MSB IN LSB IN LSB OUT BIT 6 ... 1 BIT 6 ... 1 MISO MOSI PARAMETER CONDITIONS MIN TYP MAX UNITS SCLK Period tsck 30 ns Enable Lead Time tLead 15 ns Enable Lag Time tLag 15 ns Sequential Transfer Delay ttd 30 ns Data Setup Time tsu 10 ns Data Hold Time (inputs) thi 10 ns Data Hold Time (outputs) tho 0ns Slave Access Time ta 15 ns Slave DOUT Disable Time tdis 15 ns Data Valid tv 10 ns Rise Time tr 30 ns Fall Time tf 30 ns TIMING CHARACTERISTICS(1)(2) At –40 °C to +85°C, +V DD = +2.7V, VREF = +2.5V, unless otherwise noted. TSC2200 NOTES: (1) All input signals are specified with tr = tf = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. (2) See timing diagram below. |
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