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GS82583ED18GK-675 Datasheet(PDF) 3 Page - GSI Technology |
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GS82583ED18GK-675 Datasheet(HTML) 3 Page - GSI Technology |
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3 / 26 page  GS82583ED18/36GK-675/625/550/500 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.06 8/2017 3/26 © 2014, GSI Technology 8M x 36 Pinout (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 A VDD VDDQ VDD VDDQ NC (RSVD) MCL (CFG) MCL ZQ PZT1 VDDQ VDD VDDQ VDD B VSS Q35 VSS D35 MVQ MCH (B4M) NC (RSVD) MCH (SIOM) PZT0 D0 VSS Q0 VSS C Q26 VDDQ D26 VDDQ VSS SA VDD SA VSS VDDQ D9 VDDQ Q9 D VSS Q34 VSS D34 SA VDDQ SA VDDQ SA D1 VSS Q1 VSS E Q25 VDDQ D25 VDD VSS SA VSS SA VSS VDD D10 VDDQ Q10 F VSS Q33 VSS D33 SA VDD VDDQ VDD SA D2 VSS Q2 VSS G Q24 Q32 D24 D32 VSS SA MZT1 SA VSS D3 D11 Q3 Q11 H Q23 VDDQ D23 VDDQ SA VDDQ W VDDQ SA VDDQ D12 VDDQ Q12 J VSS Q31 VSS D31 VSS SA VSS SA VSS D4 VSS Q4 VSS K CQ1 VDDQ VREF VDD KD1 VDD CK VDD KD0 VDD VREF VDDQ CQ0 L CQ1 VSS QVLD1 VSS KD1 VDDQ CK VDDQ KD0 VSS QVLD0 VSS CQ0 M VSS Q22 VSS D22 VSS SA VSS SA VSS D13 VSS Q13 VSS N Q30 VDDQ D30 VDDQ DLL VDDQ R VDDQ MCH VDDQ D5 VDDQ Q5 P Q29 Q21 D29 D21 VSS SA MZT0 SA VSS D14 D6 Q14 Q6 R VSS Q20 VSS D20 MCH VDD VDDQ VDD RST D15 VSS Q15 VSS T Q28 VDDQ D28 VDD VSS SA VSS SA VSS VDD D7 VDDQ Q7 U VSS Q19 VSS D19 NC (576 Mb) VDDQ NC (RSVD) VDDQ NC (1152 Mb) D16 VSS Q16 VSS V Q27 VDDQ D27 VDDQ VSS NUI (x18) VDD NUI (B2) VSS VDDQ D8 VDDQ Q8 W VSS Q18 VSS D18 TCK MCL NC (RSVD) MCL TMS D17 VSS Q17 VSS Y VDD VDDQ VDD VDDQ TDO ZT NC (RSVD) MCL TDI VDDQ VDD VDDQ VDD Notes: 1. Pins 6W, 7A, 8W, and 8Y must be tied Low in this device. 2. Pins 5R and 9N must be tied High in this device. 3. Pin 6A is defined as mode pin CFG in the pinout standard. It must be tied Low in this device to select x36 configuration. 4. Pin 8B is defined as mode pin SIOM in the pinout standard. It must be tied High in this device to select Separate I/O configuration. 5. Pin 6B is defined as mode pin B4M in the pinout standard. It must be tied High in this device to select Burst-of-4 configuration. 6. Pin 6V is defined as address pin SA for x18 devices. It is unused in this device, and must be left unconnected or driven Low. 7. Pin 8V is defined as address pin SA for B2 devices. It is unused in this device, and must be left unconnected or driven Low. 8. Pin 5U is reserved as address pin SA for 576 Mb devices. It is a true no connect in this device. 9. Pin 9U is reserved as address pin SA for 1152 Mb devices. It is a true no connect in this device. |
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