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GS81313LD36GK-833I Datasheet(PDF) 9 Page - GSI Technology |
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GS81313LD36GK-833I Datasheet(HTML) 9 Page - GSI Technology |
9 / 26 page GS81313LD18/36GK-833/714/625 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.13 7/2016 9/26 © 2014, GSI Technology Input Timing These devices utilize three pairs of positive and negative input clocks, CK & CK and KD[1:0] & KD[1:0], to latch the various synchronous inputs. Specifically: CK latches all address (SA) inputs. CK latches all control (R, W) inputs. KD[1:0] and KD[1:0] latch particular write data (D) inputs, as follows: • KD0 and KD0 latch D[17:0] in x36, and D[8:0] in x18. • KD1 and KD1 latch D[35:18] in x36, and D[17:9] in x18. Output Timing These devices provide two pairs of positive and negative output clocks (aka “echo clocks”), CQ[1:0] & CQ[1:0], whose timing is tightly aligned with read data in order to enable reliable source-synchronous data transmission. These devices utilize a PLL to control output timing. When the PLL is enabled, it generates 0 and 180 phase clocks from CK that control read data output clock (CQ, CQ), read data (Q), and read data valid (QVLD) output timing, as follows: • CK+0 generates CQ[1:0], CQ[1:0], Q1 active, and Q2 inactive. • . CK+180 generates CQ[1:0], CQ[1:0], Q1 inactive, Q2 active, and QVLD active/inactive. Note: Q1 and Q2 indicate the first and second pieces of read data transferred in any given clock cycle during Read operations. When the PLL is enabled, CQ is aligned to an internally-delayed version of CK. See the AC Timing Specifications for more information. CQ[1:0] and CQ[1:0] align with particular Q and QVLD outputs, as follows: • CQ0 and CQ0 align with Q[17:0], QVLD0 in x36 devices, and Q[8:0], QVLD0 in x18 devices. • CQ1 and CQ1 align with Q[35:18], QVLD1 in x36 devices, and Q[17:9], QVLD0 in x18 devices. |
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