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TMS320C6202BGNY300 Datasheet(PDF) 2 Page - Texas Instruments |
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TMS320C6202BGNY300 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 105 page TMS320C6202, TMS320C6202B FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS104I − OCTOBER 1999 − REVISED MARCH 2004 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Table of Contents parameter measurement information 47 . . . . . . . . . . . . . . . signal transition levels 47 . . . . . . . . . . . . . . . . . . . . . . . . . . timing parameters and board routing analysis 48 . . . . . . input and output clocks 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . asynchronous memory timing 52 . . . . . . . . . . . . . . . . . . . . . synchronous-burst memory timing 56 . . . . . . . . . . . . . . . . . synchronous DRAM timing 59 . . . . . . . . . . . . . . . . . . . . . . . . HOLD/HOLDA timing 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . reset timing 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . external interrupt timing 67 . . . . . . . . . . . . . . . . . . . . . . . . . . expansion bus synchronous FIFO timing 68 . . . . . . . . . . . . expansion bus asynchronous peripheral timing 70 . . . . . . expansion bus synchronous host-port timing 74 . . . . . . . . expansion bus asynchronous host-port timing 80 . . . . . . . XHOLD/XHOLDA timing 82 . . . . . . . . . . . . . . . . . . . . . . . . . . multichannel buffered serial port timing 84 . . . . . . . . . . . . . DMAC, timer, power-down timing 96 . . . . . . . . . . . . . . . . . . JTAG test-port timing 98 . . . . . . . . . . . . . . . . . . . . . . . . . . . . mechanical data 99 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . revision history 103 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GJL, GNZ, GLS, and GNY BGA packages 3 . . . . . . . . . . . . description 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . device characteristics 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C62x device compatibility 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . functional and CPU (DSP core) block diagram 9 . . . . . . . . . CPU (DSP core) description 10 . . . . . . . . . . . . . . . . . . . . . . . memory map summary 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . peripheral register descriptions 13 . . . . . . . . . . . . . . . . . . . . . DMA synchronization events 18 . . . . . . . . . . . . . . . . . . . . . . . interrupt sources and interrupt selector 19 . . . . . . . . . . . . . . signal groups description 20 . . . . . . . . . . . . . . . . . . . . . . . . . . signal descriptions 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . development support 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . documentation support 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . clock PLL 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power-down mode logic 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . power-supply sequencing 43 . . . . . . . . . . . . . . . . . . . . . . . . . . IEEE 1149.1 JTAG compatibility statement 45 . . . . . . . . . . . absolute maximum ratings over operating case temperature ranges 46 . . . . . . . . . . . . . . . . . . . . . . . . . . recommended operating conditions 46 . . . . . . . . . . . . . . . . . electrical characteristics over recommended ranges of supply voltage and operating case temperature 46 |
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